Verilog vs VHDL

[NFagan]

All,

Any advice as to using VHDL or Verilog to learn FPGA programming. I have a
background in C programming and did some hardware design back in the days
when IC's still had legs ;+).

Nick Fagan

 

[glen herrmannsfeldt]

NFagan wrote:

Any advice as to using VHDL or Verilog to learn FPGA programming. I have a
background in C programming and did some hardware design back in the days
when IC's still had legs ;+).

There is some belief that C programmers prefer verilog.

It is not that it is like C, but it has similar philosophy,
such as not being wordy when it doesn't need to be.

VHDL is much more wordy, some make an analogy to ADA, possible
to Pascal. It has, for example, more strict typing rules than
verilog does.

-- glen

 

[General Schvantzkoph]

On Mon, 09 Aug 2004 23:48:30 +0000, NFagan wrote:

All,

Any advice as to using VHDL or Verilog to learn FPGA programming. I have a
background in C programming and did some hardware design back in the days
when IC's still had legs ;+).

Nick Fagan

Verilog is much more concise then VHDL making it easier to both write and
read. It lacks the strong typing of VHDL which I think is a feature, but
VHDL programmers will tell you is a bug. In the US Verilog is dominant
except in defense sector which still uses VHDL. In Europe VHDL is more
popular.

 

[Jim Lewis]

NFagan wrote:

Any advice as to using VHDL or Verilog to learn FPGA programming. I have a
background in C programming and did some hardware design back in the days
when IC's still had legs ;+).

General Schvantzkoph wrote:

Verilog is much more concise then VHDL making it easier to both write and
read. It lacks the strong typing of VHDL which I think is a feature, but
VHDL programmers will tell you is a bug. In the US Verilog is dominant
except in defense sector which still uses VHDL. In Europe VHDL is more
popular.

Verilog is dominant in the US ASIC market.


VHDL is dominant in the US FPGA market.
VHDL owns the US defense sector.
VHDL is dominant in all markets outside of US.
Good thing for VHDL that FPGAs are taking over .


In Verilog, the operators and if statements are
similar to C. For the if statement rather than
use "{" and "}", Verilog uses "begin" and "end".
All else is different.
Do you remember what the ^ operator is?


In VHDL, the logic operators are more verbose:
and, or, not, xor, nand, nor (yikes)
others are similar: +, -,
The if statements are more verbose they always use
"then" and end with "end if".
The constants are like C string and character
constants. Following the next revision of VHDL,
I expect many of the conciseness issues with VHDL
to be gone or perhaps even superior (is_x() in VHDL
vs. is_unknown() in Verilog).

It lacks the strong typing of VHDL which I think is a
feature, but VHDL programmers will tell you is a bug.
According to a conference paper done by Tensilica,

who imposes VHDL's strong typing rules on _Verilog_ by
using a lint tool, 75% of the time when strong typing
rules are violated, it is an error. However, if you like
this feature of VHDL, you can get it in Verilog by buying
an additional tool (and help inflate the Verilog $$$ market
statistics).


HDL choice for some is like religion. Obviously people
have been successful with both. Both have their issues
otherwise there would be one clear winner.


If you intend to use your new skill to get a job,
I would encourage you to take a different approach.
Look around at who has jobs in the area you want to
work. Find out which language the your top several
choices use and learn that.

Alternately if you are a hobbiest, look around at who
else is doing what you are doing and use that (there
will be more free stuff that way).

Cheers,
Jim Lewis
P.S.
If you want to start a real flame fest, post this to
comp.lang.vhdl also.
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Jim Lewis]

BTW, if you decide on Verilog, see Cliff's papers on
Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!
RTL Coding Styles That Yield Simulation and Synthesis Mismatches

which are available at: http://www.sunburst-design.com/papers/


If you decide on VHDL, see my paper on:
VHDL Math Tricks of the Trade (strong typing made simple)

which is available at: http://www.synthworks.com/papers/

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Just an Illusion]

Hi NFagan,

NFagan wrote:

All,

Any advice as to using VHDL or Verilog to learn FPGA programming. I have a
background in C programming and did some hardware design back in the days
when IC's still had legs ;+).

Nick Fagan




In addition with any previous remarks, note that in big development the

both languages are used.

If you have some specific technology cells, you can use some vhdl vital
version for simulation, but verilog version for synthesis.

Lot of time, you have a behavioral vhdl fumctional model, and a mixed
version at the end for synthesis.

I think that you can learn quickly the syntax of Verilog with your C
background; but if you have well understand what is hardware design and
what you want to design, you can easily use VHDL too.
Don't forget that at the end, you have something that must handle
binary/boolean logic. Some sw programming way must be replace by boolean
logic version.
Example : To compare 2 bit-vectors (A, B) values

sw :
A-B = 0 ?

hdl (vhdl/verilog) :
A xor B = 0 ?


JaI

 

[Marty]

"NFagan" <nikfagan@columbus.rr.com> wrote in message
news:i3URc.7748$cT6.7066@fe2.columbus.rr.com...

All,

Any advice as to using VHDL or Verilog to learn FPGA programming. I have
a
background in C programming and did some hardware design back in the days
when IC's still had legs ;+).

Learn them both. Design and implement some HW function in both languages.
Start with VHDL, then move to Verilog. In the end, you'll know which one
YOU like better and you'll know both HDLs, which can't hurt.

FWIW, I stated with VHDL in my first ASIC design experience and now work
mostly with Verilog. Having used them both for design and simulation, I can
tell you that I'd much rather use Verilog than VHDL. I even went through
the whole "Verilog will let you compile THAT without an error?!" stage.
Howefer, in Verilog, you can code, compile and simulate to catch an error
about as fast as you can figure out which type conversion is allowed to get
rid of your compile error in VHDL - and those are not even functional
errors - just type rules! Okay, that's a stretch, but VHDL, with all its
typing, can be painful - IMO.

HTH.
--
Marty

 

[Joe]

Marty wrote:

"NFagan" <nikfagan@columbus.rr.com> wrote in message
news:i3URc.7748$cT6.7066@fe2.columbus.rr.com...

All,

Any advice as to using VHDL or Verilog to learn FPGA programming. I have

a

background in C programming and did some hardware design back in the days
when IC's still had legs ;+).


Learn them both. Design and implement some HW function in both languages.
Start with VHDL, then move to Verilog. In the end, you'll know which one
YOU like better and you'll know both HDLs, which can't hurt.

FWIW, I stated with VHDL in my first ASIC design experience and now work
mostly with Verilog. Having used them both for design and simulation, I can
tell you that I'd much rather use Verilog than VHDL. I even went through
the whole "Verilog will let you compile THAT without an error?!" stage.
Howefer, in Verilog, you can code, compile and simulate to catch an error
about as fast as you can figure out which type conversion is allowed to get
rid of your compile error in VHDL - and those are not even functional
errors - just type rules! Okay, that's a stretch, but VHDL, with all its
typing, can be painful - IMO.

HTH.
--
Marty

Strongly agreed.
I have to use both at work, escpecially on large projects
than got 3rd parties IP cores. Some parts use VHDL and some parts use
verilog. (It drive me crazy sometimes,I keep typing verilog in VHDL
fils and putting VHDL in verilog!)

I came across a book long time ago that got examples in both languages.
I can't remember the name now, but I think it worth getting that if
you decide to learn both languages. You can also download the Actel
coding guide that got simple examples of both languages:
http://www.actel.com/documents/hdlcode.pdf

Joe

 

[john jakson]

Joe <joe_y@invalid_address.nospam.com> wrote in message news:<cfe7i8$i4t$1$8300dec7@news.demon.co.uk>...

Marty wrote:
"NFagan" <nikfagan@columbus.rr.com> wrote in message
news:i3URc.7748$cT6.7066@fe2.columbus.rr.com...

All,

Any advice as to using VHDL or Verilog to learn FPGA programming. I have

a

background in C programming and did some hardware design back in the days
when IC's still had legs ;+).


Learn them both. Design and implement some HW function in both languages.
Start with VHDL, then move to Verilog. In the end, you'll know which one
YOU like better and you'll know both HDLs, which can't hurt.

FWIW, I stated with VHDL in my first ASIC design experience and now work
mostly with Verilog. Having used them both for design and simulation, I can
tell you that I'd much rather use Verilog than VHDL. I even went through
the whole "Verilog will let you compile THAT without an error?!" stage.
Howefer, in Verilog, you can code, compile and simulate to catch an error
about as fast as you can figure out which type conversion is allowed to get
rid of your compile error in VHDL - and those are not even functional
errors - just type rules! Okay, that's a stretch, but VHDL, with all its
typing, can be painful - IMO.

HTH.
--
Marty



Strongly agreed.
I have to use both at work, escpecially on large projects
than got 3rd parties IP cores. Some parts use VHDL and some parts use
verilog. (It drive me crazy sometimes,I keep typing verilog in VHDL
fils and putting VHDL in verilog!)

I came across a book long time ago that got examples in both languages.
I can't remember the name now, but I think it worth getting that if
you decide to learn both languages. You can also download the Actel
coding guide that got simple examples of both languages:
http://www.actel.com/documents/hdlcode.pdf

Joe

You mean

HDL Chip Design, A Practical Guide for Designing, Synthesizing and Simulating
ASICs and FPGAs using VHDL or Verilog by Douglas J Smith

A truly great investment but a bit stiff in $
example source in V & V and nice schematics and explanations

regards

johnjakson_usa_com

 

[Joe]

john jakson wrote:

Joe <joe_y@invalid_address.nospam.com> wrote in message news:<cfe7i8$i4t$1$8300dec7@news.demon.co.uk>...

Strongly agreed.
I have to use both at work, escpecially on large projects
than got 3rd parties IP cores. Some parts use VHDL and some parts use
verilog. (It drive me crazy sometimes,I keep typing verilog in VHDL
fils and putting VHDL in verilog!)

I came across a book long time ago that got examples in both languages.
I can't remember the name now, but I think it worth getting that if
you decide to learn both languages. You can also download the Actel
coding guide that got simple examples of both languages:
http://www.actel.com/documents/hdlcode.pdf

Joe


You mean

HDL Chip Design, A Practical Guide for Designing, Synthesizing and Simulating
ASICs and FPGAs using VHDL or Verilog by Douglas J Smith

A truly great investment but a bit stiff in $
example source in V & V and nice schematics and explanations

regards

johnjakson_usa_com

Yes, that's the one. Thanks
And as you said, it is a bit expensive :-(

Joe

 

[y_p_w]

"Marty" <m_piet@yah00.com> wrote in message news:<10hko5nsj37nkd3@corp.supernews.com>...

"NFagan" <nikfagan@columbus.rr.com> wrote in message
news:i3URc.7748$cT6.7066@fe2.columbus.rr.com...
All,

Any advice as to using VHDL or Verilog to learn FPGA programming. I have
a
background in C programming and did some hardware design back in the days
when IC's still had legs ;+).

Learn them both. Design and implement some HW function in both languages.
Start with VHDL, then move to Verilog. In the end, you'll know which one
YOU like better and you'll know both HDLs, which can't hurt.

FWIW, I stated with VHDL in my first ASIC design experience and now work
mostly with Verilog. Having used them both for design and simulation, I can
tell you that I'd much rather use Verilog than VHDL. I even went through
the whole "Verilog will let you compile THAT without an error?!" stage.
Howefer, in Verilog, you can code, compile and simulate to catch an error
about as fast as you can figure out which type conversion is allowed to get
rid of your compile error in VHDL - and those are not even functional
errors - just type rules! Okay, that's a stretch, but VHDL, with all its
typing, can be painful - IMO.

I took a couple of HDL classes in grad school. The first was VHDL
followed by the Verilog equivalent the next quarter. I prefer Verilog
if I have a choice.

That being said, it's been invaluable that I can code and debug in
both Verilog and VHDL. Limiting a combined design to only VHDL or
Verilog isn't all that practical these days. Some open source or
commercial IP is only available in one language. Learn how to use
a mixed-language simulator (Cadence NC-Affirma for example), and
you'll be all set.

The one thing I do like about VHDL is the ability to build a state
machine with types instead of fixed state assignments. Most
waveform viewers let me see the actual RTL state name. The
downside is that it makes it nearly impossible to debug a gate-
level FSM, since the state encoding is chosen by the synthesis
tool.

 

[vhdlcohen]

y_p_w@hotmail.com (y_p_w) wrote in message

...
The one thing I do like about VHDL is the ability to build a state
machine with types instead of fixed state assignments. Most
waveform viewers let me see the actual RTL state name. The
downside is that it makes it nearly impossible to debug a gate-
level FSM, since the state encoding is chosen by the synthesis
tool.
SystemVerilog has a lot of features that were adopted from VHDL

including structures (records) and enumerated data types. Actually
SystemVerilog has many new features that facilitate design definition
and verification, like interfaces and assertions, among other things.
For assertions, one can also use PSL. VHDL200x will also support many
new features that you would like. See the accelera site
http://www.accellera.com/
Ben
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* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
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* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
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* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
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