Verilog vs VHDL for Loops

A

Andre Bonin

Guest
Hey all, I'me trying to convert a C algorithm to Verilog using Quartus
II Web edition.

The following for loop doesn't compile because it says its not of
constant loop time.

What i really need is to be able to calculate the loop time "on the fly".

Can VHDL or Verilog do this? or is this a limitation?


Thanks
Error: Verilog HDL For Statement error at XXXXXXXX.v(49): must use only
constant expressions in terminating conditions

---- Error at while loop -
integer X = 0;
always
begin
while( X < 30 )
begin
X = X + 1;
end
end
 
Hi Andre,
I presume because you've posted this to CAF you're writing this code for
synthesis. In that case you should really be thinking about what you want
synthesised.
In your C algorithm, a number X is stored in a memory location somewhere.
When it's incremented, the CPU or whatever fetches the value, adds one, and
writes it back.
Now, in the synthesised version, the number X is actually implemented as a
piece of hardware. In your FPGA there's a 5 bit counter, which increments
when it gets a clock. Do you see the fundamental difference? You need to
code for this hardware. For a start, looking at your verilog code, where's
your clock?
Good luck mate, Syms.

"Andre Bonin" <Yoyoma_2@[at-]Hotmail.com> wrote in message
news:5KP2d.38134$%S.33263@pd7tw2no...
Hey all, I'me trying to convert a C algorithm to Verilog using Quartus
II Web edition.

The following for loop doesn't compile because it says its not of
constant loop time.

What i really need is to be able to calculate the loop time "on the fly".

Can VHDL or Verilog do this? or is this a limitation?


Thanks
Error: Verilog HDL For Statement error at XXXXXXXX.v(49): must use only
constant expressions in terminating conditions

---- Error at while loop -
integer X = 0;
always
begin
while( X < 30 )
begin
X = X + 1;
end
end
Click to expand...
 
Andre,

I do agree with Symon, specially if you have a software background. Be
careful when trying to synthesize (HARDWARE) your software.

Anyway, below is an example of how to implement a while_loop in VHDL.
I added some comments reagarding the conditions under which the
whil_loop is implemented;

library ieee;
use ieee.std_logic_1164.all;

entity while_ex is
port( clk: in std_logic;
z: out boolean);
end;

architecture beh of while_ex is

begin
-- while-loops are synthesizable as long as they have a
-- valid wait statement in every possible path within the loop
-- if a while-loop does not have a single wait statement, and
-- it is bound by constantes, then the tool synthesized the
-- design correctly
process -- no sensitivity list

variable x: integer range 0 to 35;
begin
x:= 0;
wait until clk'event and clk='1';
z<= false;
wh_loop: WHILE x < 30 LOOP
wait until clk'event and clk='1';
x:= x+1;
END LOOP;

z <= true;

end process;

end beh;

regards,

cristian
 
cristian wrote:

Andre,

I do agree with Symon, specially if you have a software background. Be
careful when trying to synthesize (HARDWARE) your software.
Click to expand...
The goal of the project is ADPCM encoding and a 10x10 integer matrix
multiplication, i think that could be done within the FPGA. it would be
*nice* to be able to implement any C algo within hardware but i do
accept their are limitations. Though for some odd reason VHDL seems
more apt and less 'picky' about these kinds of loops. Or am i being
deceived?

Anyway, below is an example of how to implement a while_loop in VHDL.
I added some comments reagarding the conditions under which the
whil_loop is implemented;
Click to expand...
Thank you for this piece of code, it helps me get started and play
around with VHDL. VHDL seems more 'higher level' then verilog. For
this type of task, do you reccomend VHDL or Verilog? VHDL is an older
standard but my work with verilog gives me the hint that its lower level.


library ieee;
use ieee.std_logic_1164.all;

entity while_ex is
port( clk: in std_logic;
z: out boolean);
end;

architecture beh of while_ex is

begin
-- while-loops are synthesizable as long as they have a
-- valid wait statement in every possible path within the loop
-- if a while-loop does not have a single wait statement, and
-- it is bound by constantes, then the tool synthesized the
-- design correctly
process -- no sensitivity list

variable x: integer range 0 to 35;
begin
x:= 0;
wait until clk'event and clk='1';
z<= false;
wh_loop: WHILE x < 30 LOOP
wait until clk'event and clk='1';
x:= x+1;
END LOOP;

z <= true;

end process;

end beh;

regards,

cristian
Click to expand...
 
On Sun, 2004-09-19 at 18:04 +0000, Andre Bonin wrote:
cristian wrote:

Andre,

I do agree with Symon, specially if you have a software background. Be
careful when trying to synthesize (HARDWARE) your software.

The goal of the project is ADPCM encoding and a 10x10 integer matrix
multiplication, i think that could be done within the FPGA. it would be
*nice* to be able to implement any C algo within hardware but i do
accept their are limitations. Though for some odd reason VHDL seems
more apt and less 'picky' about these kinds of loops. Or am i being
deceived?

Anyway, below is an example of how to implement a while_loop in VHDL.
I added some comments reagarding the conditions under which the
whil_loop is implemented;

Thank you for this piece of code, it helps me get started and play
around with VHDL. VHDL seems more 'higher level' then verilog. For
this type of task, do you reccomend VHDL or Verilog? VHDL is an older
standard but my work with verilog gives me the hint that its lower level.
snip
Click to expand...

There is always Handel-C which supports most of the C constructs
(for, while, arrays, pointers, functions, etc) in FPGA hardware.
 
Andre Bonin wrote:
cristian wrote:

Andre,

I do agree with Symon, specially if you have a software background. Be
careful when trying to synthesize (HARDWARE) your software.

The goal of the project is ADPCM encoding and a 10x10 integer matrix
multiplication, i think that could be done within the FPGA. it would be
*nice* to be able to implement any C algo within hardware but i do
accept their are limitations. Though for some odd reason VHDL seems
more apt and less 'picky' about these kinds of loops. Or am i being
deceived?
Click to expand...
I think you are being deceived. I have coded in both VHDL and Verilog
and have seen little difference in the two other than syntax. Both are
capable of coding the same structures in similar ways.


Anyway, below is an example of how to implement a while_loop in VHDL.
I added some comments reagarding the conditions under which the
whil_loop is implemented;

Thank you for this piece of code, it helps me get started and play
around with VHDL. VHDL seems more 'higher level' then verilog. For
this type of task, do you reccomend VHDL or Verilog? VHDL is an older
standard but my work with verilog gives me the hint that its lower level.
Click to expand...
A piece of code is not really going to help you understand your problem
or how to code in HDL. You need to consider that an HDL is just that, a
Hardware Description Language and *NOT* a software programming
language. I know that not everyone thinks or works like I do, but I
find I fight the language much less if I design my hardware in my head
or on paper and then use the HDL to describe my hardware.

If you want to do a matrix operation, you really need to design the
hardware to do that, then code that hardware. Just trying to write a
software description of the problem will not in general give you a
reasonable solution in the generated hardware.

So think about the architecture you expect and then learn how to
describe that hardware in your chosen HDL. Directly translating C to
HDL is not a good way to go.

You might even think about getting some assistance from a consultant or
a training class. I found a little bit of training to go a long way
with HDLs.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
Andre Bonin wrote:

cristian wrote:

I do agree with Symon, specially if you have a software background. Be
careful when trying to synthesize (HARDWARE) your software.

The goal of the project is ADPCM encoding and a 10x10 integer matrix
multiplication, i think that could be done within the FPGA. it would be
*nice* to be able to implement any C algo within hardware but i do
accept their are limitations. Though for some odd reason VHDL seems
more apt and less 'picky' about these kinds of loops. Or am i being
deceived?
Click to expand...
(snip)

Well, you can code a processor in VHDL, or use an FPGA that
includes one, and then you can run any C algorithm on it.

10x10 matrix multiply in combinatorial logic is a little large
even for today's FPGAs. Multiplying two 10x10 matrices is
10000 multiplies. Did you want to synthesize 10000 multipliers?

I believe ADPCM encoders are well understood and not hard
to implement, though I don't happen to know how to do it.

Are the words coming in one at a time, one per clock cycle?
How much work do you need to do on each cycle? Implement
the hardware to do just that.

Often the implementation of an algorithm, or even the algorithm
itself is completely different done in hardware than in C.

-- glen
 
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:414E757B.4AB4DBDB@yahoo.com...

A piece of code is not really going to help you understand your problem
or how to code in HDL. You need to consider that an HDL is just that, a
Hardware Description Language and *NOT* a software programming
language. I know that not everyone thinks or works like I do, but I
find I fight the language much less if I design my hardware in my head
or on paper and then use the HDL to describe my hardware.

If you want to do a matrix operation, you really need to design the
hardware to do that, then code that hardware. Just trying to write a
software description of the problem will not in general give you a
reasonable solution in the generated hardware.

So think about the architecture you expect and then learn how to
describe that hardware in your chosen HDL. Directly translating C to
HDL is not a good way to go.
Click to expand...

I agree entirely with this, every time I start a new VHDL module the
first thing I do is sketch out the hardware on a piece of paper,
then write the HDL to describe it.


Nial

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
Cyclone Based 'Easy PCI' proto board
www.nialstewartdevelopments.co.uk
 
This loop should compile fine in Synplify.

Andre Bonin wrote:
Hey all, I'me trying to convert a C algorithm to Verilog using Quartus
II Web edition.

The following for loop doesn't compile because it says its not of
constant loop time.

What i really need is to be able to calculate the loop time "on the fly".

Can VHDL or Verilog do this? or is this a limitation?


Thanks
Error: Verilog HDL For Statement error at XXXXXXXX.v(49): must use only
constant expressions in terminating conditions

---- Error at while loop -
integer X = 0;
always
begin
while( X < 30 )
begin
X = X + 1;
end
end
Click to expand...
 
Ken McElvain wrote:

This loop should compile fine in Synplify.
Click to expand...
I'me using quartus2. What is synplify?


Andre Bonin wrote:

Hey all, I'me trying to convert a C algorithm to Verilog using Quartus
II Web edition.

The following for loop doesn't compile because it says its not of
constant loop time.

What i really need is to be able to calculate the loop time "on the fly".

Can VHDL or Verilog do this? or is this a limitation?


Thanks
Error: Verilog HDL For Statement error at XXXXXXXX.v(49): must use
only constant expressions in terminating conditions

---- Error at while loop -
integer X = 0;
always
begin
while( X < 30 )
begin
X = X + 1;
end
end
Click to expand...
 
Andre Bonin a écrit:
Ken McElvain wrote:

This loop should compile fine in Synplify.


I'me using quartus2. What is synplify?
Click to expand...
QuertusII doesn't like VHDL while loops. I replaced one with a for loop
and an exit statement and it worked OK.
I don't know if it is the same with Verilog while loops though.


--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/
 
Nicolas Matringe <nicolasmatringe001@numeri-cable.fr> wrote in message news:<414FD415.5080508@numeri-cable.fr>...
Andre Bonin a écrit:
Ken McElvain wrote:

This loop should compile fine in Synplify.


I'me using quartus2. What is synplify?

QuertusII doesn't like VHDL while loops. I replaced one with a for loop
and an exit statement and it worked OK.
I don't know if it is the same with Verilog while loops though.
Click to expand...
I haven't used Synplify in ages, but I use Precision all the time.
According to the Precision manual, "Loops must be bounded by constants
or contain [a] @(posedge clk) statement."

The original poster's code:

integer X = 0;
always begin
while (X < 30) begin
X = X + 1;
end // while
end // always

has a couple of problems. First, if one were to simulate this, one
would see that it actually would execute in zero time. How SHOULD
this be implemented in hardware?

The initializer is ignored (think about it: what's the synthesizer
supposed to do with it?). The while statement isn't bounded like the
usual for loop:

for (x = 0; x < 30; x = x + 1) begin ... end //

Note the constants in that for loop, tho'. Say you had:

integer first, last;

for (x = first; x < last; x = x + 1) begin

those values aren't bounded, either, so the synthesizer wouldn't know
what to do with it.

The manual does say that the two loop conditions are ORed, so it one
modified the original poster's code as follows:

always @(posedge clk) begin
while (X < 30) begin
X = X + 1;
end // while
end // always

then one would expect things to "work." (It's a simple incrementer
that stops when it hits the value 30. Not very useful unless it can
be reset!)

Think hardware ...

-a
 
Andre Bonin wrote:
Ken McElvain wrote:

This loop should compile fine in Synplify.


I'me using quartus2. What is synplify?
Click to expand...
Synplify is a commercial FPGA synthesis tool
See: http://www.synplicity.com for details.
I'm obviously biased, but I think it is the best FPGA
synthesis tool available.

- Ken

Andre Bonin wrote:

Hey all, I'me trying to convert a C algorithm to Verilog using
Quartus II Web edition.

The following for loop doesn't compile because it says its not of
constant loop time.

What i really need is to be able to calculate the loop time "on the
fly".

Can VHDL or Verilog do this? or is this a limitation?


Thanks
Error: Verilog HDL For Statement error at XXXXXXXX.v(49): must use
only constant expressions in terminating conditions

---- Error at while loop -
integer X = 0;
always
begin
while( X < 30 )
begin
X = X + 1;
end
end
Click to expand...
 
Synplify internally transforms for loops into while
loops for synthesis. Loops (while or for) without
event controls can be synthesisized as long as the terminating
condition can be determined (this is known as the
halting problem). Synplify can figure this out for
quite complex loops. In the example, there is a
problem with the lack of initialization of the variable X
inside the always block that makes it difficult to compute
the termination condition.

Either type of loop, while or for, can also be synthesized
when all paths through the loop are broken by an event
control.

An event control is the @(posedge clk) refered to below.

Andy Peters wrote:

Nicolas Matringe <nicolasmatringe001@numeri-cable.fr> wrote in message news:<414FD415.5080508@numeri-cable.fr>...

Andre Bonin a écrit:

Ken McElvain wrote:


This loop should compile fine in Synplify.


I'me using quartus2. What is synplify?

QuertusII doesn't like VHDL while loops. I replaced one with a for loop
and an exit statement and it worked OK.
I don't know if it is the same with Verilog while loops though.


I haven't used Synplify in ages, but I use Precision all the time.
According to the Precision manual, "Loops must be bounded by constants
or contain [a] @(posedge clk) statement."

The original poster's code:

integer X = 0;
always begin
while (X < 30) begin
X = X + 1;
end // while
end // always

has a couple of problems. First, if one were to simulate this, one
would see that it actually would execute in zero time. How SHOULD
this be implemented in hardware?

The initializer is ignored (think about it: what's the synthesizer
supposed to do with it?). The while statement isn't bounded like the
usual for loop:

for (x = 0; x < 30; x = x + 1) begin ... end //

Note the constants in that for loop, tho'. Say you had:

integer first, last;

for (x = first; x < last; x = x + 1) begin

those values aren't bounded, either, so the synthesizer wouldn't know
what to do with it.

The manual does say that the two loop conditions are ORed, so it one
modified the original poster's code as follows:

always @(posedge clk) begin
while (X < 30) begin
X = X + 1;
end // while
end // always

then one would expect things to "work." (It's a simple incrementer
that stops when it hits the value 30. Not very useful unless it can
be reset!)

Think hardware ...

-a
Click to expand...
 
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