Z
zlotawy
Guest
HEllo,
I have the same component written in verilog and vhdl.
--------------------------------
entity COMP is
port(
CLK: in std_logic;
WE :in std_logic;
W_ADDR :in std_logic_vector(5 downto 0);
R_ADDR :in std_logic_vector(5 downto 0);
DIN :in std_logic_vector(7 downto 0);
DOUT
ut std_logic_vector(7 downto 0)
);
end COMP ;
architecture Behavioral of COMP is
type cube_array is array(2**6-1 downto 0) of std_logic_vector(7 downto 0);
--type cube_array is array(natural range <> of std_logic_vector(7 downto
0);
signal sig_dout : std_logic_vector(7 downto 0);
signal s_mem : cube_array;
begin
process(CLK)
begin
if rising_edge(CLK) then
if WE='1' THEN
s_mem(conv_integer(R_ADDR)) <= din;
else
sig_dout <= s_mem(conv_integer(W_ADDR));
end if;
end if;
end process;
dout <=sig_dout;
end Behavioral;
--------------------------------
module sram (
clk, we, w_adr, r_adr, din, dout
);
parameter
a_w = 6, // parametry formalne
d_w = 8;
input clk, we;
input [a_w-1:0] w_adr, r_adr;
input [d_w-1:0] din;
output [d_w-1:0] dout;
reg [ d_w-1:0] dout;
reg [2**a_w-1:0] s_mem[7:0];
always @(posedge clk)
if (we) s_mem[r_adr] <= din;
else dout <= s_mem[w_adr];
endmodule----------------------------and afer synthesize for vhdl I got
Maximum Frequency: 339.732MHzand for verilog I got Maximum Frequency:
438.308MHz.Device is 2vp30-5ff1152.Why are there differences?Thanks,zlotawy
I have the same component written in verilog and vhdl.
--------------------------------
entity COMP is
port(
CLK: in std_logic;
WE :in std_logic;
W_ADDR :in std_logic_vector(5 downto 0);
R_ADDR :in std_logic_vector(5 downto 0);
DIN :in std_logic_vector(7 downto 0);
DOUT
ut std_logic_vector(7 downto 0));
end COMP ;
architecture Behavioral of COMP is
type cube_array is array(2**6-1 downto 0) of std_logic_vector(7 downto 0);
--type cube_array is array(natural range <>
of std_logic_vector(7 downto 0);
signal sig_dout : std_logic_vector(7 downto 0);
signal s_mem : cube_array;
begin
process(CLK)
begin
if rising_edge(CLK) then
if WE='1' THEN
s_mem(conv_integer(R_ADDR)) <= din;
else
sig_dout <= s_mem(conv_integer(W_ADDR));
end if;
end if;
end process;
dout <=sig_dout;
end Behavioral;
--------------------------------
module sram (
clk, we, w_adr, r_adr, din, dout
);
parameter
a_w = 6, // parametry formalne
d_w = 8;
input clk, we;
input [a_w-1:0] w_adr, r_adr;
input [d_w-1:0] din;
output [d_w-1:0] dout;
reg [ d_w-1:0] dout;
reg [2**a_w-1:0] s_mem[7:0];
always @(posedge clk)
if (we) s_mem[r_adr] <= din;
else dout <= s_mem[w_adr];
endmodule----------------------------and afer synthesize for vhdl I got
Maximum Frequency: 339.732MHzand for verilog I got Maximum Frequency:
438.308MHz.Device is 2vp30-5ff1152.Why are there differences?Thanks,zlotawy