Verilog to VHDL conversion

J

johnp

Guest
I need to convert some Verilog files to VHDL and have looked at
assorted (free) tools. So far,
the Verilog2VHDL tool from Questa Technologies looks promising, but it
has a number of bugs.

Does anyone know if they still exist and are supporting the tool?

Can anyone suggest a better tool?

Thanks!

John Providenza
 
On 09/01/2011 07:22 AM, johnp wrote:
I need to convert some Verilog files to VHDL and have looked at
assorted (free) tools. So far,
the Verilog2VHDL tool from Questa Technologies looks promising, but it
has a number of bugs.

Does anyone know if they still exist and are supporting the tool?

Can anyone suggest a better tool?
Click to expand...
Icarus Verilog has a VHDL target code generator that is being
actively maintained.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
 
On 9/2/2011 8:17 PM, Stephen Williams wrote:
On 09/01/2011 07:22 AM, johnp wrote:
I need to convert some Verilog files to VHDL and have looked at
assorted (free) tools. So far,
the Verilog2VHDL tool from Questa Technologies looks promising, but it
has a number of bugs.

Does anyone know if they still exist and are supporting the tool?

Can anyone suggest a better tool?

Icarus Verilog has a VHDL target code generator that is being
actively maintained.
Click to expand...
Note that the Icarus VHDL target was designed for translating
synthesizable Verilog code. It is not currently and may never be a
general purpose Verilog to VHDL converter.

Cary
 
On Sep 5, 1:51 pm, "Cary R." <no-s...@host.spam> wrote:
On 9/2/2011 8:17 PM, Stephen Williams wrote:

On 09/01/2011 07:22 AM, johnp wrote:
I need to convert some Verilog files to VHDL and have looked at
assorted (free) tools. So far,
the Verilog2VHDL tool from Questa Technologies looks promising, but it
has a number of bugs.

Does anyone know if they still exist and are supporting the tool?

Can anyone suggest a better tool?

Icarus Verilog has a VHDL target code generator that is being
actively maintained.

Note that the Icarus VHDL target was designed for translating
synthesizable Verilog code. It is not currently and may never be a
general purpose Verilog to VHDL converter.

Cary
I've looked at Icarus and it's VHDL translation doesn't quite fit the
Click to expand...
bill. The Questa Technologies folks
have emailed back and look to be making updates and bug-fixes. We'll
see how they work out!

John P.
 
On Thursday, September 1, 2011 7:22:11 AM UTC-7, johnp wrote:
I need to convert some Verilog files to VHDL and have looked at
assorted (free) tools. So far,
the Verilog2VHDL tool from Questa Technologies looks promising, but it
has a number of bugs.

Does anyone know if they still exist and are supporting the tool?

Can anyone suggest a better tool?

Thanks!

John Providenza
Click to expand...


In VHDL 2008, new feature 'Hierarchical Names' was introduced, but I couldn't find an example of how to implement these Hierarchical Names in VHDL code. Even the Doulus website is not explaining it properly. Can anybody guide me on this?
You can send me email to ankit1312@gmail.com too.

Thank you.
 
Hi all,

I didn't know about the Questa tool. At some point (I think this tool is still available) X-Tek Corp had an interesting Verilog<->VHDL translator. It is not a free tool though, not sure if you can get an evaluation version.

BTW using the Icarus target feature (Verilog->VHDL only) looks interested.

Does anyone use this feature? What are essentially the capabilities of this target? It would be interesting if it can get basic synthesizable Verilog to VHDL correctly.

Best,
Nikos Kavvadias
 
On 9/17/2013 4:07 AM, Nikolaos Kavvadias wrote:

BTW using the Icarus target feature (Verilog->VHDL only) looks
interested.

Does anyone use this feature? What are essentially the capabilities
of this target? It would be interesting if it can get basic
synthesizable Verilog to VHDL correctly.
Click to expand...

The Icarus VHDL code generator was a GSOC project from a few years ago
and has had only minimal support since then. It is described on the
following web page:

http://iverilog.wikia.com/wiki/Using_VHDL_Code_Generator

Since it's free it's easy to see if it works for you. Unfortunately if
it doesn't support what you need there may not be resources available to
enhance it, but bug reports or discussions on the Icarus development
mailing list are always welcomed. At the moment the project is focusing
on fixing bugs in existing functionality, adding SystemVerilog support
and reading VHDL RTL to allow mixed language simulations.

Cary
 
There is a program called vhdl2v that converts VHDL vode to verilog code.

the program is free, you can download it from this link
http://www.ocean-logic.com/downloads.htm

this tool is not perfect, but give it a try.
 
On Thursday, September 1, 2011 at 7:52:11 PM UTC+5:30, johnp wrote:
I need to convert some Verilog files to VHDL and have looked at
assorted (free) tools. So far,
the Verilog2VHDL tool from Questa Technologies looks promising, but it
has a number of bugs.

Does anyone know if they still exist and are supporting the tool?

Can anyone suggest a better tool?

Thanks!

John Providenza
Click to expand...

can anyone help me can anyone sugguest vdhl into verilog converter
Thanks..
 
On Monday, January 20, 2014 at 3:51:22 AM UTC-8, alluupe...@gmail.com wrote:
There is a program called vhdl2v that converts VHDL vode to verilog code.

the program is free, you can download it from this link
http://www.ocean-logic.com/downloads.htm

this tool is not perfect, but give it a try.
Click to expand...

Yes, I was going to suggest this. It is quite good compared to the technology about a decade ago. And it's free!

Because it is free it is not perfect, as alley-oop said. It works best with code that is written in a Verilog-style without much VHDL abstraction. You'll have to do some hand-edit fix-ups and may have to tweak the VHDL code to get it through. Most of the errors in Verilog output result in syntax errors - so they'll be easy to find.

Good luck.
 
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