verilog to schematic problem.

[ARAVIND]

I am reading in verilog file to generate schematic view.
ICFB -> File -> IMPORT -> Verilog

The schematic generated doesnt have power and ground pins in all the
symbols till bottom of hierarchy.

I have the following options in my .ihdlEnvFile which i am loading in
the form:

DirLabel = XYZ
Target Library =ZYX
Reference Libraries =ZYX
Verilog Design Files =ZYX.V
-y Options =
Library Extn. =
-v Options =
-f Options =
Ignore Modules File =
Log File =./verilogIn.log
Work Area =/tmp
Power Net =vpwr
Ground Net =vgnd
Global Signals =
Import Modules That Match Existing Target Library Cells =true
Verilog Cell Modules =Import
Verilog Structural Modules View =schematic
Functional View Name =functional
Netlist View Name =netlist
Schematic View Name =schematic
Symbol View Name =symbol
Name Map Table = ./verilogIn.map.tables
Sheet Size =none
Pin Placement Flag =Left and Right Sides
Pin Placement File =
Label Size =0.062500
Maximum Number Of Rows =1024
Maximum Number of Columns =1024
Line-Line Spacing = 0.50000
Line-Component Spacing = 0.50000
Density Level =0
Full Place and Route =false
Fast labels =false
Minimize Cross Over =true
Generate Square Schematics =true
Extract Schematics =false
Ignore Extra Pins =true
No Dummy Nets In Netlist View =false
Verbose =true
Through CellView Library =basic
Through CellView Cell =cds_thru
Through CellView View =symbol
Pre Compiled Library =
Destination IR Lib =
ViewName for IR Library =hdl
Only Compile a Verilog Library =false

 

[Bernd Fischer]

Just a thought!

Usually power and ground are treated as globals
in Verilog and also for e.g. Std. Cell Designs.

Have you missed to define that?

Global Signals =

Bernd


ARAVIND wrote:

I am reading in verilog file to generate schematic view.
ICFB -> File -> IMPORT -> Verilog

The schematic generated doesnt have power and ground pins in all the
symbols till bottom of hierarchy.

I have the following options in my .ihdlEnvFile which i am loading in
the form:

DirLabel = XYZ
Target Library =ZYX
Reference Libraries =ZYX
Verilog Design Files =ZYX.V
-y Options =
Library Extn. =
-v Options =
-f Options =
Ignore Modules File =
Log File =./verilogIn.log
Work Area =/tmp
Power Net =vpwr
Ground Net =vgnd
Global Signals =
Import Modules That Match Existing Target Library Cells =true
Verilog Cell Modules =Import
Verilog Structural Modules View =schematic
Functional View Name =functional
Netlist View Name =netlist
Schematic View Name =schematic
Symbol View Name =symbol
Name Map Table = ./verilogIn.map.tables
Sheet Size =none
Pin Placement Flag =Left and Right Sides
Pin Placement File =
Label Size =0.062500
Maximum Number Of Rows =1024
Maximum Number of Columns =1024
Line-Line Spacing = 0.50000
Line-Component Spacing = 0.50000
Density Level =0
Full Place and Route =false
Fast labels =false
Minimize Cross Over =true
Generate Square Schematics =true
Extract Schematics =false
Ignore Extra Pins =true
No Dummy Nets In Netlist View =false
Verbose =true
Through CellView Library =basic
Through CellView Cell =cds_thru
Through CellView View =symbol
Pre Compiled Library =
Destination IR Lib =
ViewName for IR Library =hdl
Only Compile a Verilog Library =false