Verilog to Levelized Netlist

[j.vimal]

Hi
I am looking for a tool that can output a circuit in the "levelized
format" (.lev files) if the input is a verilog file.

I tried Googling, but no fruitful results. If you have or know a
software that can do it, please let me know.

Thanks.

 

[Mike Treseler]

j.vimal wrote:

I am looking for a tool that can output a circuit in the "levelized
format" (.lev files) if the input is a verilog file.

Assuming that such a format has been defined,
do you have a simulator that could
make any use of it?

Levelized compiled simulation
is a strategy for designing simulators
-- on the other side of the coin from
the event driven strategy.

-- Mike Treseler

 

[j.vimal]

Mike Treseler wrote:

j.vimal wrote:

I am looking for a tool that can output a circuit in the "levelized
format" (.lev files) if the input is a verilog file.

Assuming that such a format has been defined,
do you have a simulator that could
make any use of it?

Yes, I have written a zero-delay / unit-delay circuit simulator.

I wanted the "level" format because it is easy to parse and maintain
the data structure of the circuit internally.

Levelized compiled simulation
is a strategy for designing simulators
-- on the other side of the coin from
the event driven strategy.

Actually, the simulator which I had written uses queues to process
events!


-- Vimal