verilog testbench fot vhdl ams

[apurva]

hi all,

i want to use the signal values used in RTL verilog testbench to drive
the signals in my vhdl-ams model.
how ca i do this in advanced ms?

can anyone please help?

regards
apurva

 

[Ajeetha (www.noveldv.com)]

On Feb 6, 6:59 pm, "apurva" <agarwal.apu...@gmail.com> wrote:

hi all,

i want to use the signal values used in RTL verilog testbench to drive
the signals in my vhdl-ams model.
how ca i do this in advanced ms?

can anyone please help?

regards
apurva

If your simulator supports mixed mode simulation, this should be
straight forward. If not you will need to rewrite Verilog TB to VHDL
which shouldn't be that hard either.

Regards
Ajeetha, CVC
www.noveldv.com