verilog task synthesis

[Nahum Barnea]

Hi.


I have a synthesizable verilog code that it's size could be reduced,
if I would use tasks and only change the parameters when I call the
task.

The problem is that I am afraid from synthesis missmathes with
simulation.

Does anyone here have experience with verilog task synthesis?

Does the following example make sense ?

module example(
input[3:0] wire i, j,
input wire clk,
output[3:0] reg out2 );

always@(posedge clk)
begin
or_task(i, j);
end

task or_task;
input a, b;
begin
out2 <= i | j;
end
endtask
endmodule

 

[Vinilkant Tejaswi]

The real problem is that input i and j should be assigned proper
values at each edge. Calling tasks in the testbench is the most
appropriate usage for tasks. Since i and j will not have correct
values by using this method. This would not run correctly, however it
might be synthesizeable. I hope that helps.

vinil

 

[Bob Hoffman]

I use tasks in synthesis and have had no problems. Simulation
matches and verplex has no problem with this. However, I was
not using v2k extensions.

My usage is mostly in state machine construction.


"Nahum Barnea" <nahum_barnea@yahoo.com> wrote in message
news:fc23bdfc.0503090920.7ce0240f@posting.google.com...

Hi.


I have a synthesizable verilog code that it's size could be reduced,
if I would use tasks and only change the parameters when I call the
task.

The problem is that I am afraid from synthesis missmathes with
simulation.

Does anyone here have experience with verilog task synthesis?

Does the following example make sense ?

module example(
input[3:0] wire i, j,
input wire clk,
output[3:0] reg out2 );

always@(posedge clk)
begin
or_task(i, j);
end

task or_task;
input a, b;
begin
out2 <= i | j;
end
endtask
endmodule

 

[Rob Dekker]

"Nahum Barnea" <nahum_barnea@yahoo.com> wrote in message news:fc23bdfc.0503090920.7ce0240f@posting.google.com...

Hi.


I have a synthesizable verilog code that it's size could be reduced,
if I would use tasks and only change the parameters when I call the
task.

The problem is that I am afraid from synthesis missmathes with
simulation.

Synthesis tools will complain if you write something non-synthesizable.
If they don't, it is considered 'bad-logic', which is a critical bug for tool developers.

Your biggest enemy (with Verilog tasks) might not be simulation-synthesis mismatch,
but might be the tricky behavior of local variables (and outputs) in Verilog tasks (which are 'static' between task calls).

You can get 'latch' behavior and very strange logic if you don't always assign something
to task outputs (under every condition).
Problem gets worse if you call the task from multiple always blocks.

Just DONT use local variables and outputs before you assign to them.

Same problems (and worse, because of the function variable itself being 'static') are there for Verilog functions.

Does anyone here have experience with verilog task synthesis?