verilog task calling

Z

zinga

Guest
Hi,
I am having tasks in a particular module in a test bench setup and want to
call those tasks in another module. The question is can I do so by
hierarchical referencing as I do it on signls or do I have to do something
else.

thanks.
 
On Mon, 11 Oct 2004 07:15:41 -0400, "zinga" <zingafriend@yahoo.com>
wrote:

Hi,
I am having tasks in a particular module in a test bench setup and want to
call those tasks in another module. The question is can I do so by
hierarchical referencing as I do it on signls or do I have to do something
else.

thanks.

Hmmm...

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From: "zinga" <zingafriend@yahoo.com
Newsgroups: comp.lang.verilog
Subject: verilog task calling
Date: Mon, 11 Oct 2004 07:15:41 -0400
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uzma, meet zinga. zinga, meet uzma. You two seem to have a lot in
common, perhaps you can get together and work this out?

--
Rich Webb Norfolk, VA
 
"zinga" <zingafriend@yahoo.com> wrote in message news:<537553408abecff0c77c6d1e001e11a0@localhost.talkaboutprogramming.com>...
Hi,
I am having tasks in a particular module in a test bench setup and want to
call those tasks in another module. The question is can I do so by
hierarchical referencing as I do it on signls or do I have to do something
else.
Yes, you can use a hierarchical reference to a task name in a task call.
This will not be supported by synthesis tools, but should work in the
testbench in a simulator.
 

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