M
masini
Guest
Hello,
anyone know how I could call a verilog task through a VHDL Testbench?
I have a protected Verilog modul with an VHDL interface. I have built a
Tesbench in VHDL. But now I need also to call the task in the protected
Verilog.
I think in Verilog Testbench would do it so:
<instance_name>.task_name;
And in VHDL???
Thank you very much.
Masini
anyone know how I could call a verilog task through a VHDL Testbench?
I have a protected Verilog modul with an VHDL interface. I have built a
Tesbench in VHDL. But now I need also to call the task in the protected
Verilog.
I think in Verilog Testbench would do it so:
<instance_name>.task_name;
And in VHDL???
Thank you very much.
Masini