verilog task call in vhdl

hi all

Assume we have the DUT in VHDL and the BFM/Monitor/Checker in Verilog.
Aim is
to have the Test Bench & test cases in VHDL. how do we call the Verilog
BFM
tasks from the VHDL test cases.

regards
vinay

 

vinay.k22914125@gmail.com wrote:

Assume we have the DUT in VHDL and the BFM/Monitor/Checker in Verilog.
Aim is
to have the Test Bench & test cases in VHDL. how do we call the Verilog
BFM
tasks from the VHDL test cases.

Assuming that your simulator does not allow directly calling Verilog
tasks from VHDL, you can probably still kludge around it. You could
put an always block in the Verilog code that waits for a change on a
particular signal, and then calls the task, passing the values of other
signals as arguments. The VHDL code can then put the desired argument
values onto the signals, and then trigger the signal that the always
block is waiting on. It is clumsy, but it should work.