verilog task and vhdl

[carlob]

Hi all,
I've a functional model of a PHY chip in verilog with a lot of tasks t
stimualte change on signals at the interface (and not only)...
Unfortunately I'm not experienced with verilog...I would write a testbenc
in vhdl and reuse the model in verilog...

How to call a verilog task inside a vhdl testbench??? Is it possible???
would like to don't change the verilog (that has already been teste
deeply) and reusing it as it is...

Thank you for the help
Carlo

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[RCIngham]

Hi all,
I've a functional model of a PHY chip in verilog with a lot of tasks to
stimualte change on signals at the interface (and not only)...
Unfortunately I'm not experienced with verilog...I would write
testbench
in vhdl and reuse the model in verilog...

How to call a verilog task inside a vhdl testbench??? Is it possible??? I
would like to don't change the verilog (that has already been tested
deeply) and reusing it as it is...

Thank you for the help
Carlo

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If the Verilog task is inside a Verilog module, then you can instantiat
the module just like a VHDL component. You will need a componen
declaration in VHDL that matches the Verilog module's port declaration.


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[carlob]

If the Verilog task is inside a Verilog module, then you can instantiate
the module just like a VHDL component. You will need a component
declaration in VHDL that matches the Verilog module's port declaration.


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Thank you for the answer....
Ok...I can instantiate the module inside vhdl...but then what is the sinta
to call tasks???

For example:
in verilog I have:
module PHY{...}

and inside the module
task pippo; ...

Inside vhdl I do a component declarartion and a port map...
component PHY
port(...);
end component;

then

myphy: PHY
port map(...);

...now I want to call task pippo...

myphy.pippo ???
pippo ???

Thank you for the help
Carlo

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[Mike Treseler]

On 6/3/2011 3:24 AM, carlob wrote:

If the Verilog task is inside a Verilog module, then you can instantiate
the module just like a VHDL component. You will need a component
declaration in VHDL that matches the Verilog module's port declaration.


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Thank you for the answer....
Ok...I can instantiate the module inside vhdl...but then what is the sintax
to call tasks???

For example:
in verilog I have:
module PHY{...}

I suggest a direct instance - no component,
Something like:

phy_1 : entity work.phy
port map (reset => reset_s, -- [in]
clock => clock_s, -- [in]
data => data_s, -- [out]
ready => ready_s); -- [out]


-- Mike Treseler

 

[carlob]

On 6/3/2011 3:24 AM, carlob wrote:
If the Verilog task is inside a Verilog module, then you ca
instantiate
the module just like a VHDL component. You will need a component
declaration in VHDL that matches the Verilog module's por
declaration.


---------------------------------------
Posted through http://www.FPGARelated.com


Thank you for the answer....
Ok...I can instantiate the module inside vhdl...but then what is th
sintax
to call tasks???

For example:
in verilog I have:
module PHY{...}


I suggest a direct instance - no component,
Something like:

phy_1 : entity work.phy
port map (reset => reset_s, -- [in]
clock => clock_s, -- [in]
data => data_s, -- [out]
ready => ready_s); -- [out]


-- Mike Treseler

Thank you for your answer....
The main question is, when phy_1 is instanciated into vhdl testbench, ho
to call the task defined inside the module???
I haven't tried till now something like this...suppose module PHY has
task defined blabla...how can I call it???
simply blabla
or phy_1.blabla
or it is not possible....

Thank you for help...
Carlo



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[Mike Treseler]

I suggest a direct instance - no component,
Something like:

phy_1 : entity work.phy
port map (reset => reset_s, -- [in]
clock => clock_s, -- [in]
data => data_s, -- [out]
ready => ready_s); -- [out]


-- Mike Treseler

On 6/3/2011 1:48 PM, carlob wrote:

Thank you for your answer....
The main question is, when phy_1 is instantiated into vhdl testbench, how
to call the task defined inside the module???

I the instanced task can only be called from inside the module.
A test task would have to be declared in the testbench.

-- Mike Treseler

 

[carlob]

I the instanced task can only be called from inside the module.
A test task would have to be declared in the testbench.

-- Mike Treseler

On the internet I read about writing a verilog wrapper that trigger task
using its input signals....then instanciate that wrapper into vhd
testbench and move tasks by triggering signals....

Otherwise...I should write the testbench in verilog....

Another question is...I use modelsim...is there any issue related to mixe
language (vhdl-verilog) simulation that must be considered....
It should be useful to know it before starting....

Thank you for help...
Carlo

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[Alan Fitch]

On 04/06/11 21:23, carlob wrote:

I the instanced task can only be called from inside the module.
A test task would have to be declared in the testbench.

-- Mike Treseler



On the internet I read about writing a verilog wrapper that trigger tasks
using its input signals....then instanciate that wrapper into vhdl
testbench and move tasks by triggering signals....

Otherwise...I should write the testbench in verilog....

Another question is...I use modelsim...is there any issue related to mixed
language (vhdl-verilog) simulation that must be considered....
It should be useful to know it before starting....

Thank you for help...
Carlo

The first thing I would do is read the chapter "Mixed Language
Simulation" in the Modelsim User Guide. For instance, Modelsim 10.0a
supports VHDL external names (hierarchical names), but only from VHDL to
VHDL, not from VHDL to Verilog.

So I suspect some kind of triggering would be required.

The other practical issue is whether you have a mixed-language license.

regards
Alan

--
Alan Fitch

 

[Mike Treseler]

On 6/4/2011 1:23 PM, carlob wrote:

On the internet I read about writing a verilog wrapper that trigger tasks
using its input signals....then instanciate that wrapper into vhdl
testbench and move tasks by triggering signals....
Otherwise...I should write the testbench in verilog....

That "wrapper" is a verilog testbench.

Another question is...I use modelsim...is there any issue related to mixed
language (vhdl-verilog) simulation that must be considered....
It should be useful to know it before starting....

Modelsim requires two licenses for mixed vhdl and verilog.
Your choices are:
1. Buy a license and write vhdl procedures for the verilog uut.
2. Learn verilog and write a verilog testbench.
3. Write your own phy model in vhdl.

-- Mike Treseler

 

[carlob]

That "wrapper" is a verilog testbench.

Yes you are right...

Another question is...I use modelsim...is there any issue related t
mixed
language (vhdl-verilog) simulation that must be considered....
It should be useful to know it before starting....

Modelsim requires two licenses for mixed vhdl and verilog.
Your choices are:
1. Buy a license and write vhdl procedures for the verilog uut.
2. Learn verilog and write a verilog testbench.
3. Write your own phy model in vhdl.

-- Mike Treseler

I think I will write my own phy model in vhdl taking inspiration from th
verilog one...it seems cleaner...in my opinion...

Thanks all for help
Carlo


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[Alessandro Basili]

On 6/5/2011 10:53 AM, Mike Treseler wrote:

Your choices are:
1. Buy a license and write vhdl procedures for the verilog uut.
2. Learn verilog and write a verilog testbench.
3. Write your own phy model in vhdl.

I believe there's a forth. Since the model "has already been tested
deeply" I would create the vhdl model out of the back annotation that it
certainly has (I used to do that with Designer for Actel devices).

Once you have your PHY_ba.vhd you simply include it in your simulation
and you instantiate it in your testbench as you would do normally with a
component written in vhdl.

If your PHY model never went through a post-layout simulation I hardly
doubt it was "tested deeply" and I would seriously reconsider the first
three options listed by Mike.

Al