verilog-system verilog integration

[gomsi]

I am doing a system verilog constraint random test bench. I have a up
and running test environment in verilog. Now when I try to run this
system verilog test bench into my environment I see a whole lot of
syntex error of verilog which other wise dont occur. I have used the
-sverilog switch for VCS also. Can somebody please suggest how to mix
the verilog and system verilog compilation so as not to encounter such
problems

 

[Ajeetha]

Hi,
My guess is that your Verilog code uses SV reserved words such as
"do/priority" etc. Show us few errors to say more solidly. If so, refer
to:

http://www.synopsys.com/links/va_mar05.html?BAC-va&Link=VA_Home_Mar05_Issue

Basically you need to use switches like: +systemverilogext+.sv etc.

HTH
Ajeetha, CVC
www.noveldv.com

gomsi wrote:

I am doing a system verilog constraint random test bench. I have a up
and running test environment in verilog. Now when I try to run this
system verilog test bench into my environment I see a whole lot of
syntex error of verilog which other wise dont occur. I have used the
-sverilog switch for VCS also. Can somebody please suggest how to mix
the verilog and system verilog compilation so as not to encounter such
problems

 

gomsi wrote:

I am doing a system verilog constraint random test bench. I have a up
and running test environment in verilog. Now when I try to run this
system verilog test bench into my environment I see a whole lot of
syntex error of verilog which other wise dont occur.

The most likely cause is the large number of new keywords added in
SystemVerilog, many of which match commonly used identifier names in
legacy Verilog code.

The IEEE SystemVerilog and Verilog-2005 standards try to deal with this
by adding new compiler directives `begin_keywords and `end_keywords.
These are used to select the keyword set of a particular language
version, for the code between them, to get backward compatibility. For
example, `begin_keywords "1364-1995" sets the keywords reserved by the
parser to the set reserved in Verilog-1995, for the code that follows.

It may not be the ideal solution for you, but it should be portable
across all tools that are compliant with the standards.