Verilog System Tasks and Functions

Hi,

In VHDL i have used a signal spy init_signal_spy("/sys/A", "B",0),
what is the equivalent in verilog?

B is the signal in current module.

Is there any equivalent in verilog to read the signal deep in
heriarchy.

S

 

[Ajeetha]

Interesting question, almost the first time I am hearing this - Verilog
allows much easier way for this, just do:

$display ("My internal signal is %0d", sys.A);

i.e. a "DOT" operator allows you to navigate through the design
hierarchy.

HTH
Ajeetha, CVC
www.noveldv.com

sarma.nedunuri@gmail.com wrote:

Hi,

In VHDL i have used a signal spy init_signal_spy("/sys/A", "B",0),
what is the equivalent in verilog?

B is the signal in current module.

Is there any equivalent in verilog to read the signal deep in
heriarchy.

S

 

Thanks,

I will try and think this helps.

S

Ajeetha wrote:

Interesting question, almost the first time I am hearing this - Verilog
allows much easier way for this, just do:

$display ("My internal signal is %0d", sys.A);

i.e. a "DOT" operator allows you to navigate through the design
hierarchy.

HTH
Ajeetha, CVC
www.noveldv.com

sarma.nedunuri@gmail.com wrote:
Hi,

In VHDL i have used a signal spy init_signal_spy("/sys/A", "B",0),
what is the equivalent in verilog?

B is the signal in current module.

Is there any equivalent in verilog to read the signal deep in
heriarchy.

S