Verilog Synthesis using dc_shell

[Sreekumar]

Hi,

I have a set of verilog files, each implementing a unit of my entire
design. We can assume my entire unit to implement a big combinational
circuit which uses mutiplexers, adders etc. I would like to synthesize
the entire design for optimal timing (ie., I dont care for the area, I
want the fastest design). I would also like to save the entire
synthesized design to a file. In this file the netlist must be
flattened ie., there should no hierarchy in the netlist. Every unit
in my design (ie., the adders, multiplesers etc) has to be expanded as
gates and written to the file in verilog format.

Can anyone help me out how to go about doing it. My dc_shell script
looks like this

/*read the design*/

read -f verilog mux.v
read -f verilog adder.v
read -f verilog decoder.v
read -f verilog myDesign.v
set_operating_conditions WCCOM
set_wire_load_model -name "10x10" -library class
create_clock tclk -nameclk -period 19

uniquify
ungroup -all -flatten
compile -map_effort high
write -format verilog -output ./design-syn.v

I execute this script using the following command

dc_shell>include script.scr



I am not sure if my conditions will give me the best synthesized logic
for timing. Also I want only one module in the final synthesized file
design-syn.v and it should have only gates, which is not happening.

Thanks for the help in advance

Sreekumar

 

[Metin Yerlikaya]

Hi,
you should have one top level design which instantiates all other
sub blocks.
Assuming your top level design is myDesign, you should specify the
current design before you start to compile. Assuming "read" command
has
a integrated elaborate command also and the latest design you read
according to below script is your top level design. And you should
check for errors or missing elements before you start to compile with
"check_design" and "link"
command. If "check_design" brings an "Error" you cannot compile. Also
after executing the "link" command, check if anything is missing. Any
you miss in the
lower level of hiearchy will be a black box because dc has no
information about it. After link and check_design is clean you should
be able to sythesize the whole design and flatten it or not as you
wish.
If you meet the timing? you can have the answer after compile is
finished.
Execute report_timing or report_constraints -all_violaters or
something.
Once again fix the Errors first than compile.


vksreekumar@gmail.com (Sreekumar) wrote in message news:<a571c2b1.0408191157.14db48f7@posting.google.com>...

Hi,

I have a set of verilog files, each implementing a unit of my entire
design. We can assume my entire unit to implement a big combinational
circuit which uses mutiplexers, adders etc. I would like to synthesize
the entire design for optimal timing (ie., I dont care for the area, I
want the fastest design). I would also like to save the entire
synthesized design to a file. In this file the netlist must be
flattened ie., there should no hierarchy in the netlist. Every unit
in my design (ie., the adders, multiplesers etc) has to be expanded as
gates and written to the file in verilog format.

Can anyone help me out how to go about doing it. My dc_shell script
looks like this

/*read the design*/

read -f verilog mux.v
read -f verilog adder.v
read -f verilog decoder.v
read -f verilog myDesign.v
set_operating_conditions WCCOM
set_wire_load_model -name "10x10" -library class
create_clock tclk -nameclk -period 19

uniquify
ungroup -all -flatten
compile -map_effort high
write -format verilog -output ./design-syn.v

I execute this script using the following command

dc_shell>include script.scr



I am not sure if my conditions will give me the best synthesized logic
for timing. Also I want only one module in the final synthesized file
design-syn.v and it should have only gates, which is not happening.

Thanks for the help in advance

Sreekumar