Verilog synthesis down to asic level

Hello.
I have a question about Verilog synthesis and what opinions you
experienced engineers out there have. I'm interessted in using verilog
as entry and for simulating then prototyping on fpga, then to take that
design down to cell based asic or custom asic. Im not going to layout
this by hand so i wonder what options are there and how good are they.
Price is also an issue. I only know about Synopsys Design Compiler and
Ic compiler. Can anybody explain what i would need in this case and how
the general designflow is?

Im a student and are very interessted in starting design of custom
projects myself..

-
Thomas

 

[Mike Treseler]

cumulusnimbus@gmail.com wrote:

I'm interessted in using verilog
as entry and for simulating then prototyping on fpga, then to take that
design down to cell based asic or custom asic.

I would focus on the front end.
Until you have all your rtl code
running correctly in simulation
it is hard to make an intelligent
choice about devices.

-- Mike Treseler

 

Ok. Deciding on fpga, cell based or custom is a descision process i
understand.
I may have explained myself a little bit confusing. Lets say i have a
project with verilog rtl code wich is verified and tested. But the real
testing could not be finished before DC or whatever designtool can
backannotate timing etc. Lets say I now want this produced as asic. How
would i do this? Cell or custom i guess are just two branches in a
tree. The thing i realy want to know is.
What can i use DC for here and would i need additional tools? To what
level does DC take me. And for what parts do i need other tools? I
first undestood DC to be a fully rtl synthesis tool that could create
netlist, do routing etc and finnaly produce mask layout of chip? But
this is not the case? I saw a product called Ic compiler wich was next
step after DC. But what does IC do and what does DC to. Did not find
any good explanation.

Cheers
Thomas

 

[Mike Treseler]

cumulusnimbus@gmail.com wrote:

Lets say i have a
project with verilog rtl code wich is verified and tested.
But the real
testing could not be finished before DC or whatever designtool can
backannotate timing etc.

Consider writing the code and verifying it
before you start worrying about the next step.
Remove all of the logical errors first.
This will take longer than you think.

But the real
testing could not be finished before DC or whatever designtool can
backannotate timing etc. Lets say I now want this produced as asic. How
would i do this?

When you have working code, call in the vendors
and have them demo their backend tools on your code.
This puts you in a strong position. No smoke.
Their tools either work for you or they don't.

-- Mike Treseler

 

[svtechie@gmail.com]

Thomas, this process requires lots of detail but I am going to keep in
brief here. Typical steps in ASIC design includes

1. System Architecture
Very important step - We can assume it is already done. It involves
defining performance criteria for design, how much memory, clock speed
etc. Now if you are targetting FPGA, your performance parameters are
going to be different from ASIC performance parameters. You may have to
know the relation (loosely) before end.

2. RTL coding
Implement the design. Generally if design is ultimately targetted
to ASIC, optimize design for ASIC process.. Who cares about fpga!!
But if design is targetted to FPGA, you may have to
optimize/partition design for FPGA. Also pay attn to coding style.

3. Functional simulation
Verify the correctness of the RTL

4. Lint
Verify if coding style dosn't introduce bugs at synthesis stages.
(what you see in simulation may not be implemented by synthesis tools)

5. FPGA Synthesis/Routing - simple

6. ASIC synthesis, clock tree insertion, DFT insertion, ATPG testing,
reset tree insertion, timing analysis
7. Back End - Place & Route, timing analysis, DFT analysis, DRC checks
etc

Step 6 & step 7 are fairely complicated and it is safe to assume that
there are multiple experts handling the whole flow. Tools are also
costly ~ $500K total. Though you can experiment with university tools.

thx
- svtechie
www.svtechie.com