Y
yiannis
Guest
Hello everybody,
I am working on a Verilog project,and after having sg that it is
correctly simulated,i tried to synthesize it, but there are a lot of
warnings....
Can you propose me a webpage,or better, a book which is considered
to be really helpful for writing synthesizable Verilog code?
Thanks in advance,
Yiannis
I am working on a Verilog project,and after having sg that it is
correctly simulated,i tried to synthesize it, but there are a lot of
warnings....
Can you propose me a webpage,or better, a book which is considered
to be really helpful for writing synthesizable Verilog code?
Thanks in advance,
Yiannis