verilog syntax question

[Jason Zheng]

Is there a quick way to express that we want certain bits of an
expression but not all of them?

e.g., I want the last 2 bits of A[1:0] + 1

Or do I have to declare another wire and assign the result to it?

 

[Arjuna Wijesurendra]

Jason Zheng wrote:

Is there a quick way to express that we want certain bits of an
expression but not all of them?

e.g., I want the last 2 bits of A[1:0] + 1

Or do I have to declare another wire and assign the result to it?

Bitwise anding the expression with n'b11..11 will of course mask off all
other bits leaving only the last n. Eg: (A[1:0] + 1) & 2'b11. Beware
however that the resulting expression will still be as long as the
longer of the two operands to '&', which in the case of your example
will be 32bits because of the integer 1; the result contains the last 2
bits you wanted, only it'll be padded with zeros to make it 32 bits
long. Did you want a result expression length equal to the number of
bits you want extracted?

Getting at certain bits of an expression in general (ie. not necessarily
the last n bits) can be more tedious:

Eg to get the 6th to 3rd bits incl of A[1:0] + 1, ((A[1:0] + 1) &
7'b1111000) >> 3.

Any other ideas?

AW