verilog Syntax check

[Yang Luo]

I'm using modelsim se 10.1c. I find that modelsim for syntax checking is not strict.
There are some examples:
1) I use default settings to build a project. There is no error or warning whenn compiling but I used an undefined variable, only when simulating the signal is red line.
Example code:
input [D_SIZE: 0] i_a;
wire signed [D_SIZE: 0] w_a;
assign w_ia = i_a;
2) When using unassigned variable , the same situation with above.
Example code:
wire signed [D_SIZE: 0] w_ib;
wire signed [D_SIZE: 0] w_id;
wire signed [D_SIZE: 0] w_bd;
assign w_bd = w_ib - w_id;
Question:
How should I do to get more strict syntax checking in modelsim? If modelsim cannot get strict checking, is there other software can do?
Another question:
Modelsim rebuilding and cleanup project, how to operate? how to operate that I can know the compilation is all recompiled?

 

[Alan Fitch]

On 08/06/15 13:32, Yang Luo wrote:

I'm using modelsim se 10.1c. I find that modelsim for syntax checking is not strict.
There are some examples:
1) I use default settings to build a project. There is no error or warning whenn compiling but I used an undefined variable, only when simulating the signal is red line.
Example code:
input [D_SIZE: 0] i_a;
wire signed [D_SIZE: 0] w_a;
assign w_ia = i_a;

That's a feature of Verilog (implicit nets).
You have three options

1. run your code through a synthesis tool

2. add

`default_nettype none

to the top of your file

3. Use a better language

2) When using unassigned variable , the same situation with above.
Example code:
wire signed [D_SIZE: 0] w_ib;
wire signed [D_SIZE: 0] w_id;
wire signed [D_SIZE: 0] w_bd;
assign w_bd = w_ib - w_id;

That is perfectly legal code. A synthesis tool will remove the whole
design, so again a simple solution is to synthesize the code.


kind regards
Alan

Question:
How should I do to get more strict syntax checking in modelsim? If modelsim cannot get strict checking, is there other software can do?
Another question:
Modelsim rebuilding and cleanup project, how to operate? how to operate that I can know the compilation is all recompiled?

--
Alan Fitch

 

[Allan Herriman]

On Mon, 08 Jun 2015 05:32:44 -0700, Yang Luo wrote:

I'm using modelsim se 10.1c. I find that modelsim for syntax checking is
not strict.
There are some examples:
1) I use default settings to build a project. There is no error or
warning whenn compiling but I used an undefined variable, only when
simulating the signal is red line.
Example code:
input [D_SIZE: 0] i_a;
wire signed [D_SIZE: 0] w_a;
assign w_ia = i_a;
2) When using unassigned variable , the same situation with above.
Example code:
wire signed [D_SIZE: 0] w_ib;
wire signed [D_SIZE: 0] w_id;
wire signed [D_SIZE: 0] w_bd;
assign w_bd = w_ib - w_id;
Question:
How should I do to get more strict syntax checking in modelsim? If
modelsim cannot get strict checking, is there other software can do?
Another question:
Modelsim rebuilding and cleanup project, how to operate? how to operate
that I can know the compilation is all recompiled?

Try adding the line

Show_Lint = 1

to the [vlog] section of the modelsim.ini file.

Regards,
Allan

 

[GaborSzakacs]

Alan Fitch wrote:
[snip]

2. add

`default_nettype none

to the top of your file

If you plan to use any third party Verilog modules in your
design, I would suggest also adding:

`default_nettype wire

to the bottom of your file. The reason is that like macros,
`default_nettype is global and retains its value for the
next file compilation. Other code that is expecting implicit
net creation will break if compiled after your module unless
you add this line at the end to return the default net type
to the Verilog default of wire.

Some other caveats:

`default_nettype should only change outside the module
definition.

The standard Verilog 2001 port definitions also need to
have the net type explicitly stated. i.e.

module foo
(
input bar,
output baz,
output reg flub
);

Would need to change to:

`default_nettype none

module foo
(
input wire bar,
output wire baz,
output reg flub
);

--
Gabor