Verilog Synopsys script

[Arash Arfaee]

Hi
I have two verilog files, containing two parts of a design. I need to
test it with different amount of delays at input/output of one of the
modules.
Any suggestions?
I'm trying to set input/output/clock delay by using script commands
like set_min_delay or something similar to that. Does nybody have
anyidea how to do this. here are my inputs/outputs for this module:

module s_m (
clk,
reset,
address,
lb,
gr
);


input [7:0] address;
input lb, clk, reset;

output gr;

Thanks.

Cheers,
Arash

 

[Mike Treseler]

Arash Arfaee wrote:

I have two verilog files, containing two parts of a design. I need to
test it with different amount of delays at input/output of one of the
modules.
Any suggestions?

If you mean latency, use a programmable pipeline.
If you mean analog delays, use static timing analysis.

-- Mike Treseler