Verilog Switch Level Modeling

[manoj]

Hi,

I have one question regarding the switch level modeling. Is it
possible to convert the bi-directional gates (tran, tranif0, rtranif0,
etc...) to unidirectional gates? If user has written such kind of
gates in his design then is it possible to figure out what kind of bi-
directional gates can be converted into unidirectional gates? What is
the criteria for such kind of conversion? I am asking this question
from optimization point of view.

Thanks
Manoj

 

[manoj]

On Apr 16, 9:48 pm, manoj <manoj...@gmail.com> wrote:

Hi,

I have one question regarding the switch level modeling. Is it
possible to convert the bi-directional gates (tran, tranif0, rtranif0,
etc...) to unidirectional gates? If user has written such kind of
gates in his design then is it possible to figure out what kind of bi-
directional gates can be converted into unidirectional gates? What is
the criteria for such kind of conversion? I am asking this question
from optimization point of view.

Thanks
Manoj

Hello Verilog Experts,

I am looking for a reply. Is it possible to treat tran as
unidirectional tran gate instead of bi-directional tran?

If yes, then under what condition we can treat tran as unidirectional
tran gate?

Thanks
Manoj

 

[glen herrmannsfeldt]

manoj <manojmeh@gmail.com> wrote:

On Apr 16, 9:48 pm, manoj <manoj...@gmail.com> wrote:

I have one question regarding the switch level modeling. Is it
possible to convert the bi-directional gates (tran, tranif0, rtranif0,
etc...) to unidirectional gates? If user has written such kind of
gates in his design then is it possible to figure out what kind of bi-
directional gates can be converted into unidirectional gates? What is
the criteria for such kind of conversion? I am asking this question
from optimization point of view.
(snip)

I am looking for a reply. Is it possible to treat tran as
unidirectional tran gate instead of bi-directional tran?

If yes, then under what condition we can treat tran as
unidirectional tran gate?

If one side is only inputs, then it is possible, other
wise it isn't. A tran gate could be used in place of
the more usual tri-state or open collector (drain) logic,
which would make it unidirectional. It could also be used
between two tristate nets, in which case it must be
treated as bidirectional.

But there should be no reason to design using tran gates unless
one wanted to use the bidirectional mode, or at least for a
tri-state or open collector (open drain by now) state.

In days long past, I believe that pass transistors were used
as a way to reduce the size of some logic operations.

That works better in the case of PMOS or NMOS logic, with pullups,
though. For CMOS, the only use I could see would be tristate
for internal nodes, or open drain for output drivers.

-- glen

 

On Apr 19, 1:38 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:

If one side is only inputs, then it is possible, other
wise it isn't.

Or if one side is only outputs, assuming you don't care about the
(incorrect) value of that side since there are no inputs reading it.

You need the direction from each of the outputs to each of the inputs.
If that requires both directions, then you need bidirectional. If
that
only requires one direction, then you can get by with unidirectional
in
that direction.

If you have a network of tranifs, then this has to be generalized so
a transistor with an output on one side is considered an output driver
on the other side, and one with an input on one side is considered to
be an input on the other side. It is a transitive relationship that
propagates through the tranifs.

But there should be no reason to design using tran gates unless
one wanted to use the bidirectional mode, or at least for a
tri-state or open collector (open drain by now) state.

Agreed. But I have seen machine-generated code that used
bidirectionals
where unidirectionals were sufficient. Perhaps they were working from
a physical schematic/database where the originally designed direction
was
not tracked. Restoring the originally intended direction would
definitely
be a performance optimization for simulation.

 

[manoj]

Hi Experts,

Thanks for your reply.

I am new to Verilog. One basic question regarding Verilog Languague,
as per my understanding input and output keyword is just

a notion in Verilog Language. Input port can have driver as well.

What is the way to figure out that port is input port or an output
port?

Thanks
Manoj


On Apr 23, 1:54 am, sh...@cadence.com wrote:

On Apr 19, 1:38 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:



If one side is only inputs, then it is possible, other
wise it isn't.

Or if one side is only outputs, assuming you don't care about the
(incorrect) value of that side since there are no inputs reading it.

You need the direction from each of the outputs to each of the inputs.
If that requires both directions, then you need bidirectional.  If
that
only requires one direction, then you can get by with unidirectional
in
that direction.

If you have a network of tranifs, then this has to be generalized so
a transistor with an output on one side is considered an output driver
on the other side, and one with an input on one side is considered to
be an input on the other side.  It is a transitive relationship that
propagates through the tranifs.

But there should be no reason to design using tran gates unless
one wanted to use the bidirectional mode, or at least for a
tri-state or open collector (open drain by now) state.

Agreed.  But I have seen machine-generated code that used
bidirectionals
where unidirectionals were sufficient.  Perhaps they were working from
a physical schematic/database where the originally designed direction
was
not tracked.  Restoring the originally intended direction would
definitely
be a performance optimization for simulation.