F
Francisco Camarero
Guest
Because I could not find a proper power operator for verilog,
and ^ is already taken by the bitwise xor, I decided to try
VHDL's one (**):
module bug ;
parameter exp1=3;
parameter exp2=4;
integer n1;
integer n2;
initial
begin
n1 = -2**exp1;
n2 = -2**exp2;
$display("n1=%4d; n2=%4d;",n1,n2);
end
endmodule
My simulator prints out:
# n1= -8; n2= 16;
What for me seems like ** has less precedence than - , not very common I would
say.
-2**e seems to mean (-2)**e, and not -(2**e)
how do other simulators behave?
and ^ is already taken by the bitwise xor, I decided to try
VHDL's one (**):
module bug ;
parameter exp1=3;
parameter exp2=4;
integer n1;
integer n2;
initial
begin
n1 = -2**exp1;
n2 = -2**exp2;
$display("n1=%4d; n2=%4d;",n1,n2);
end
endmodule
My simulator prints out:
# n1= -8; n2= 16;
What for me seems like ** has less precedence than - , not very common I would
say.
-2**e seems to mean (-2)**e, and not -(2**e)
how do other simulators behave?