D
Denis Gleeson
Guest
Hello All
I have a problem with my simulation.
Can some one tell me whats wrong. It may be in my test bench as Im no
expert.
I have reduced the verilog so that its at its simplest.
What I find is that a signal which should be toggling in sequence with
the clock in my test bench is just not doing so.
Its the signal Int_Read_Trigger_Address_Clk in the module code. Its
just going high when the clear line goes low.
Its so simple I cant believe its not working.
Please have a look below.
------------------------- This is the test bench
--------------------------
`timescale 10ns/10ns
module Comisn_24_tst;
// Set up local variables for passing parameters to the device under
test.
// INPUTS
reg TOP_Main_clk;
reg TOP_clear;
reg TOP_Read_Trigger_Address_Clk;
comisn1_Top DUT ( TOP_Main_clk, TOP_clear, TOP_Main_clk);
initial // Test stimulus
begin
// Set initial values for all module inputs.
TOP_Main_clk = 0;
TOP_clear = 1;
TOP_Read_Trigger_Address_Clk = 0;
// Set clear line low .
#50 TOP_clear = 0;
#50000 $stop;
end
initial // Clock generator
begin
TOP_Main_clk = 0;
forever #10 TOP_Main_clk = !TOP_Main_clk;
end
always begin
#10 TOP_Read_Trigger_Address_Clk = !TOP_Read_Trigger_Address_Clk;
end
initial
$monitor($stime,,, TOP_clear,,,
TOP_Main_clk,,,TOP_Read_Trigger_Address_Clk);
endmodule
------------------------- This is the module
-----------------------------
module comisn1_Top (Main_clk, clear, Read_Trigger_Address_Clk );
input Main_clk;
input clear;
input Read_Trigger_Address_Clk;
reg Int_Read_Trigger_Address_Clk;
/////////////////////////////////////////////////////
// First Off Synchronise all external signals to
// the main clock for the system.
/////////////////////////////////////////////////////
always @ (posedge Main_clk or posedge clear)
begin
if(clear)
begin
Int_Read_Trigger_Address_Clk <= 1'b0;
end
else
begin
Int_Read_Trigger_Address_Clk <= Read_Trigger_Address_Clk;
end
end
endmodule
----------------------------------------------------------------------
Many thanks for any help in advance.
Regards
Denis
I have a problem with my simulation.
Can some one tell me whats wrong. It may be in my test bench as Im no
expert.
I have reduced the verilog so that its at its simplest.
What I find is that a signal which should be toggling in sequence with
the clock in my test bench is just not doing so.
Its the signal Int_Read_Trigger_Address_Clk in the module code. Its
just going high when the clear line goes low.
Its so simple I cant believe its not working.
Please have a look below.
------------------------- This is the test bench
--------------------------
`timescale 10ns/10ns
module Comisn_24_tst;
// Set up local variables for passing parameters to the device under
test.
// INPUTS
reg TOP_Main_clk;
reg TOP_clear;
reg TOP_Read_Trigger_Address_Clk;
comisn1_Top DUT ( TOP_Main_clk, TOP_clear, TOP_Main_clk);
initial // Test stimulus
begin
// Set initial values for all module inputs.
TOP_Main_clk = 0;
TOP_clear = 1;
TOP_Read_Trigger_Address_Clk = 0;
// Set clear line low .
#50 TOP_clear = 0;
#50000 $stop;
end
initial // Clock generator
begin
TOP_Main_clk = 0;
forever #10 TOP_Main_clk = !TOP_Main_clk;
end
always begin
#10 TOP_Read_Trigger_Address_Clk = !TOP_Read_Trigger_Address_Clk;
end
initial
$monitor($stime,,, TOP_clear,,,
TOP_Main_clk,,,TOP_Read_Trigger_Address_Clk);
endmodule
------------------------- This is the module
-----------------------------
module comisn1_Top (Main_clk, clear, Read_Trigger_Address_Clk );
input Main_clk;
input clear;
input Read_Trigger_Address_Clk;
reg Int_Read_Trigger_Address_Clk;
/////////////////////////////////////////////////////
// First Off Synchronise all external signals to
// the main clock for the system.
/////////////////////////////////////////////////////
always @ (posedge Main_clk or posedge clear)
begin
if(clear)
begin
Int_Read_Trigger_Address_Clk <= 1'b0;
end
else
begin
Int_Read_Trigger_Address_Clk <= Read_Trigger_Address_Clk;
end
end
endmodule
----------------------------------------------------------------------
Many thanks for any help in advance.
Regards
Denis