Verilog simulation of placed/routed netlist using verilog XL

[ajay.j.joshi@gmail.com]

Hi,

I want to simulate the verilog netlist of placed and routed design
obtained from Cadence SoC Encounter. I have the sdf file from SoC
Encounter. I am using Verilog XL. I used the sdf_annotate command in
my testbench as follows

initial begin
$sdf_annotate("./design.sdf",instance_name,,,,);
end

Is this the right way to do it?

Thanks in advance.

Regards,
Ajay