Verilog simulation library creation with Synopsys DC

[Milos Becvar]

Hi,

I am trying to import a design from Synopsys DC to Synopsys TetraMAX
ATPG tool, but it requires also "Verilog simulation models for all
library cells".
I was wondering wheather there is any easy way to generate a Verilog
functional simulation models for all library cells.
I found that "write_lib" command can generate simulation models in VHDL
but I have not found anything similar for Verilog.
I hope that there must be a simple way to solve this problem, besides
writing a necessary models by hand.

Many thanks for any help.

Milos Becvar

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-- Assistant Professor
-- Czech Technical University in Prague
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