Verilog Sequential Multiplier

  • Thread starter Peter Laquidara
  • Start date
P

Peter Laquidara

Guest
I am trying to find Verilog code that implements a sequential
multiplier. The data representation should be 2's complement signed
and the data width should be parametertized. My application requires
a signed multiplier that is optimized for the minimum number of gates.
The throughput is not important. Thanks for your help.
 

Welcome to EDABoard.com

Sponsor

Back
Top