Verilog reduction operator modelling in VHDL

[uday.das@gmail.com]

Hi ,
To detect whether a bit of a multibit signal is unconnected or
undriven , i.e having X or Z value in Verilog we check in a very simple
way :
^data_bus[31:0]=== 1'bX
i.e. we do XOR reduction of all the bit then comare with X, if it is
evalates to X then we know any of the bit is undriven or unconnected.

How we can model Verilog reduction operator in VHDL ? I guess by loop.
Please help me few lines of code for that ?

Thanks and regards
Uday

 

[Rolf Eike Beer]

Von uday.das@gmail.com:

Hi ,
To detect whether a bit of a multibit signal is unconnected or
undriven , i.e having X or Z value in Verilog we check in a very simple
way :
^data_bus[31:0]=== 1'bX
i.e. we do XOR reduction of all the bit then comare with X, if it is
evalates to X then we know any of the bit is undriven or unconnected.

How we can model Verilog reduction operator in VHDL ? I guess by loop.
Please help me few lines of code for that ?

function bus_connected(bus: std_logic_vector) return boolean is
begin
for i in bus'range loop
if (bus(i) /= '0') and (bus(i) /= '1') then
return true;
end if;
end loop;
return false;
end;

....
assert bus_connected(data_bus) report "data_bus has unconnected lines"
severity error;
....

Eike

 

[Jonathan Bromley]

On 13 Oct 2005 00:50:38 -0700, "uday.das@gmail.com"
<uday.das@gmail.com> wrote:

Hi ,
To detect whether a bit of a multibit signal is unconnected or
undriven , i.e having X or Z value in Verilog we check in a very simple
way :
^data_bus[31:0]=== 1'bX
i.e. we do XOR reduction of all the bit then comare with X, if it is
evalates to X then we know any of the bit is undriven or unconnected.

Or unknown.

Check out the is_unknown() function. Alternatively, as another
poster said, write the loop explicitly.

If you expect to use reduction operators extensively, you may
care to write your own functions to do it...

function and_reduce(s: std_logic_vector) return std_logic is
variable r: std_logic := '1';
begin
for i in s'range loop
r := r and s(i);
end loop;
return r;
end;

or_reduce and xor_reduce are very similar, but remember to
initialise the variable to '0'.

The upcoming VHDL-200x enhancements will probably include
native reduction operators.
--
Jonathan Bromley, Consultant

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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Rolf Eike Beer]

Von Jonathan Bromley:

The upcoming VHDL-200x enhancements will probably include
native reduction operators.

Will this include something like this?

variable foo: std_logic_vector(some range);

....

if (foo = (others => '0')) then
....

Eike

 

[uday.das@gmail.com]

Eike , Jonathan ,
Thanks a lot for your expert ideas.

Uday