verilog read file question

[Yang Luo]

When I use modelsim simulation, I write a read file module, but I cannot delay the read-data in the module (out of the module, I can delay), Is this a modelsim's bug or my code's bug? How can I put my filepath on interface? The code as follow. (my result is o_de delayed 3clk, but o_data not)
`timescale 1 ns/ 1 ps
module read_file_v #(
parameter SIZE = 8,
parameter DELAY = 3
)(
input clk,
input resetn,
input i_de,
output o_de,
output [SIZE-1:0] o_data
);

integer fp_in;
initial
begin
fp_in = $fopen("input//inY.hex","r");
end

integer fDataFlg;
reg [DELAY-1:0] ri_de ;
reg [DELAY*SIZE-1:0] ri_data;
always@(posedge clk or negedge resetn)
if(!resetn)begin
fDataFlg <= 32'd0;
ri_de[0] <= 32'd0;
ri_data[SIZE-1:0] <= 32'd0;
end
else if(!$feof(fp_in))begin
ri_de[0] <= i_de;
if(i_de)begin
fDataFlg <= $fscanf(fp_in,"%x",ri_data[SIZE-1:0]);
end
end
else begin
ri_de[0] <= i_de;
$fclose(fp_in);
end

//delay match
genvar i;
generate for(i=1;i<DELAY;i=i+1)begin:delay_i
always@(posedge clk or negedge resetn)
if(!resetn)begin
ri_de <= 32'd0;
ri_data[(i+1)*SIZE-1:i*SIZE] <= 32'd0;
end
else begin
ri_de <= ri_de[i-1];
ri_data[(i+1)*SIZE-1:i*SIZE] <= ri_data[i*SIZE-1i-1)*SIZE];
end
end
endgenerate

assign o_data = ri_data[DELAY*SIZE-1DELAY-1)*SIZE];
assign o_de = ri_de[DELAY-1];
endmodule