Verilog - Race Condition - Please Help !!

[dash82]

Thank you Gabor for your earlier comments.

I completely modified my code. I guess i am facing one final glitch. I
think my logic is correct for 1/2 rate Convolutional Encoder with
generator polynomials (1,1,1) & (1,0,1). However, I see a race
condition.

I am using "reset" variable to control the set of statements that gets
executed. However, I am seeing that all the assignment statements are
getting executed everytime, irrespective of the "reset" variable
condition.

I want to make my code synthesizable too. Any help would be greatly
appreciated. Please excuse me if this question annoys you. Still
learning.

Code:


module conencoder (out1,out2,in1,clock,reset);
output out1,out2;
input in1,clock,reset;
reg u0,u1,u2,temp_u0,temp_u1,temp_u2;
reg out1,out2;

initial
begin
//if (reset)
//begin
assign out1 = 1'b0;
assign out2 = 1'b0;
assign u0 = 1'b0;
assign u1 = 1'b0;
assign u2 = 1'b0;
assign temp_u0 = 1'b0;
assign temp_u1 = 1'b0;
assign temp_u2 = 1'b0;
//end
end

always @(clock)
begin
if (reset)
begin
//shifting the input bit through 3 registers.
assign u2 = temp_u1;
assign u1 = temp_u0;
assign u0 = in1 ;
end
else if (!reset)
begin
//performing xor operation to produce the encoded bits.
ERROR:All assignment statements are getting
//executed irrespective of "reset" variable block
checking.
assign out1 = (u2 ^ u1 ^ u0);
assign out2 = (u2 ^ u0);
assign temp_u1 = u1 ;
assign temp_u0 = u0 ;
end
end

endmodule

----------------------------------------------------------------------------------------
testbench:
--------------

module testbench ;
reg clock,reset,in1 = 1'b0;


conencoder r1(out1,out2,in1,clock,reset);

initial
begin
//clock = 1'b1;
//reset = 1'b1;
end

/*always
begin
// #30 clock = ~clock ;
end */

always
begin
#3 reset = 1'b1 ;
#2 in1 = 1'b1;
#3 clock = 1'b1 ;
#3 reset = 1'b0;
#3 clock = 1'b0;
//ERROR STARTS. After this all assignment statements seems to be
getting executed in main code.
#3 reset = 1'b1 ;
#2 in1 = 1'b1;
#3 clock = 1'b1 ;
#3 reset = 1'b0;
#3 clock = 1'b0;
#3 reset = 1'b1 ;
#2 in1 = 1'b1;
#3 clock = 1'b1 ;
#3 reset = 1'b0;
#3 clock = 1'b0;
#3 reset = 1'b1 ;
#2 in1 = 1'b1;
#3 clock = 1'b1 ;
#3 reset = 1'b0;
#3 clock = 1'b0;
#3 reset = 1'b1 ;
#2 in1 = 1'b1;
#3 clock = 1'b1 ;
#3 reset = 1'b0;
#3 clock = 1'b0;


end

endmodule

-------------------------------------------------------------------------------

The above code is compiled with ModelSim and works fine. I know I am
making some stupid mistake due to which
all 'assignment' statements are getting executed in the main code.
Please help and I apologize for a long description.

 

[mjl296@hotmail.com]

dash82 wrote:

Thank you Gabor for your earlier comments.

I completely modified my code. I guess i am facing one final glitch. I
think my logic is correct for 1/2 rate Convolutional Encoder with
generator polynomials (1,1,1) & (1,0,1). However, I see a race
condition.

I am using "reset" variable to control the set of statements that gets
executed. However, I am seeing that all the assignment statements are
getting executed everytime, irrespective of the "reset" variable
condition.

I want to make my code synthesizable too. Any help would be greatly
appreciated. Please excuse me if this question annoys you. Still
learning.

Code:


module conencoder (out1,out2,in1,clock,reset);
output out1,out2;
input in1,clock,reset;
reg u0,u1,u2,temp_u0,temp_u1,temp_u2;
reg out1,out2;

initial
begin
//if (reset)
//begin
assign out1 = 1'b0;
assign out2 = 1'b0;
assign u0 = 1'b0;
assign u1 = 1'b0;
assign u2 = 1'b0;
assign temp_u0 = 1'b0;
assign temp_u1 = 1'b0;
assign temp_u2 = 1'b0;
//end
end

always @(clock)
begin
if (reset)
begin
//shifting the input bit through 3 registers.
assign u2 = temp_u1;
assign u1 = temp_u0;
assign u0 = in1 ;
end
else if (!reset)
begin
//performing xor operation to produce the encoded bits.
ERROR:All assignment statements are getting
//executed irrespective of "reset" variable block
checking.
assign out1 = (u2 ^ u1 ^ u0);
assign out2 = (u2 ^ u0);
assign temp_u1 = u1 ;
assign temp_u0 = u0 ;
end
end

endmodule

----------------------------------------------------------------------------------------
testbench:
--------------

module testbench ;
reg clock,reset,in1 = 1'b0;


conencoder r1(out1,out2,in1,clock,reset);

initial
begin
//clock = 1'b1;
//reset = 1'b1;
end

/*always
begin
// #30 clock = ~clock ;
end */

always
begin
#3 reset = 1'b1 ;
#2 in1 = 1'b1;
#3 clock = 1'b1 ;
#3 reset = 1'b0;
#3 clock = 1'b0;
//ERROR STARTS. After this all assignment statements seems to be
getting executed in main code.
#3 reset = 1'b1 ;
#2 in1 = 1'b1;
#3 clock = 1'b1 ;
#3 reset = 1'b0;
#3 clock = 1'b0;
#3 reset = 1'b1 ;
#2 in1 = 1'b1;
#3 clock = 1'b1 ;
#3 reset = 1'b0;
#3 clock = 1'b0;
#3 reset = 1'b1 ;
#2 in1 = 1'b1;
#3 clock = 1'b1 ;
#3 reset = 1'b0;
#3 clock = 1'b0;
#3 reset = 1'b1 ;
#2 in1 = 1'b1;
#3 clock = 1'b1 ;
#3 reset = 1'b0;
#3 clock = 1'b0;


end

endmodule

-------------------------------------------------------------------------------

The above code is compiled with ModelSim and works fine. I know I am
making some stupid mistake due to which
all 'assignment' statements are getting executed in the main code.
Please help and I apologize for a long description.

As Gabor said in his last post, you will benefit from reading a
Verilog book - there are basic guidelines that should be followed to
produce synthesisable code and to avoid some of the problems you are
having, and you need to become familiar with these guidelines as well
as learning the language syntax.

Anyway;

1) Remove the initial block, it will not synthesise. The reset clause
in the always block should do this job. You should only set registers
to constants in the reset clause - your "shifting the input bit
through 3 registers" should be controlled by another signal.

2) Change always @(clock) to always @(posedge clock), otherwise your
code will execute on both clock edges, probably not what you want.

3) You do not properly understand how to assign values within the
always block. What you are doing with assign is technically legal in
some versions of Verilog, which is why it is getting through the
compiler, but it is certainly not what you want - I also understand it
to be deprecated. Change lines like this:

assign out1 = (u2 ^ u1 ^ u0);

To this...

out1 <= (u2 ^ u1 ^ u0);

And learn the difference between blocking assignments (=) and non-
blocking assignments (<=), and why it matters.

Mark