Verilog Question...

[G]

If you simulate independently "cnt_15.v", it begins counting AT the
same rising clock edge as when you assert "ce"(counter enable).

If you simulate independently "div_16M.v", it generates a "0" one clock
cycle after the last count value(1111) or at the beginning of a new
count(0000) and then resumes its high state until 1111.

Why is it when I use the "div_16M.v" module to supply the "ce" signal
for the counter module("cnt_15.v") and simulate these two modules at
the top level, does the counter begin counting one cycle after "ce" is
asserted high again? This screws up my timing at the
transition(Eventually, this will be a simple two digit LCD hex
counter...). Thanks for any help...

BTW, This is pre-fit, behavioral simulation using ModelSim...For
reference:


// Module: cnt_10.v

// This module counts from 0 to 15 and then rolls over.

module cnt_10(ce,clk,clr,tc,qout);
input ce;
input clk;
input clr;
output tc;
output [3:0] qout;

reg [3:0] count = 0; //Current count value

always @(posedge clk or posedge clr)
begin
if (clr) //asynchronous RESET active High
count <= 4'b0;
else
if (ce)
if (count==4'hF)
count <= 4'h0;
else
count <= count + 1;
else
count <= count;
end

assign qout = count;
assign tc = (count==4'hF); //Terminal count flag


endmodule



// module: div_16M.v

// This module divides the incoming 30 MHz clock by 2^24 and generates
a
// terminal count pulse of one clock width during the counter rollover.

module div_16M(clk,tc_1s);
input clk;
output tc_1s;
//output count;

reg [3:0] count = 0; //Current count value
reg tc_1s;

always @ (posedge clk)
begin
count <= count + 1;
tc_1s <= ~&count;
end

endmodule


// module: test.v

// This is the top level module that ties all sub-modules together

module test(clk,reset,tc_ones,ones_en,cnt_1s);
input clk;
input reset;
output tc_ones;
output ones_en;
output [3:0] cnt_1s;


wire nreset;
wire ones_en;
wire tens_en;
wire tc_ones;

div_16M DIV_16M(
..clk(clk),
..tc_1s(ones_en)
);

cnt_10 ONES(
..ce(ones_en),
..clk(clk),
..clr(nreset),
..tc(tc_ones),
..qout(cnt_1s)
);


assign nreset = ~reset;

endmodule

 

[glen herrmannsfeldt]

G wrote:

If you simulate independently "cnt_15.v", it begins counting AT the
same rising clock edge as when you assert "ce"(counter enable).

If you simulate independently "div_16M.v", it generates a "0" one clock
cycle after the last count value(1111) or at the beginning of a new
count(0000) and then resumes its high state until 1111.

Why is it when I use the "div_16M.v" module to supply the "ce" signal
for the counter module("cnt_15.v") and simulate these two modules at
the top level, does the counter begin counting one cycle after "ce" is
asserted high again? This screws up my timing at the
transition(Eventually, this will be a simple two digit LCD hex
counter...). Thanks for any help...

(snip)

In a synchronous system the value of a signal, such as ce, before
the clock is what counts. Before the clock edge all the logic
is evaluated and determines the value the registers will have after
the clock edge.

Most logic families now have 0 hold time FF's, so that the FF inputs
can change on the clock edge.

Now, consider your code:

always @ (posedge clk)
begin
count <= count + 1;
tc_1s <= ~&count;
end

Note that tc_1s is inside the always block. It is then evaluated
and registered by clk. It will then go low on the next clock edge
after &count is true, that is, the same edge where count<=0.

You can change this by moving it out of the always @(posedge clk),
either continuous assignment or an always block without
a posedge clk in it.

-- glen
-- glen

 

[John Penton]

G wrote:

If you simulate independently "cnt_15.v", it begins counting AT the
same rising clock edge as when you assert "ce"(counter enable).

You have not shown us how you drove the inputs to this module when you
simulated it.

If you simulate independently "div_16M.v", it generates a "0" one
clock cycle after the last count value(1111) or at the beginning of a
new count(0000) and then resumes its high state until 1111.

Why is it when I use the "div_16M.v" module to supply the "ce" signal
for the counter module("cnt_15.v") and simulate these two modules at
the top level, does the counter begin counting one cycle after "ce" is
asserted high again? This screws up my timing at the
transition(Eventually, this will be a simple two digit LCD hex
counter...). Thanks for any help...

I suspect the key to this difference is precisely _when_ ce is being driven
high. As Glen has pointed out, when you wire the two modules together, ce
is driven high _after_ the rising edge of the clock - therefore your counter
increments on the next rising edge. This is normal synchronous circuit
behaviour. I suspect that when you tested cnt_15 independently, you
arranged to assert ce just before the rising edge of the clock and therefore
the counter increments on the same cycle. This is not normal synchronous
circuit behaviour.

John

--
John Penton - posting as an individual unless otherwise indicated.