Verilog publication/user group?

[Mark Brehob]

Hello all,
Is there a reasonable place to publish short papers on Verilog coding
or common algorithms? Something like a user group or something else?
I've got a student who has come up with a fairly snazzy bit of Verilog
code that runs a lot faster than a naive implementation of the same
algorithm (pick X priority selector). It clearly isn't well suited for
an academic publication, but it seems interesting and useful enough to
be worth sharing with a larger audience (and ideally go somewhere on
his resume as an actual publication rather than a newsgroup post).

Ideas?

Thanks,
Mark Brehob

 

[Jonathan Bromley]

On Wed, 24 Feb 2010 10:28:50 -0800 (PST), Mark Brehob wrote:

Is there a reasonable place to publish short papers on Verilog coding
or common algorithms? Something like a user group or something else?
I've got a student who has come up with a fairly snazzy bit of Verilog
code that runs a lot faster than a naive implementation of the same
algorithm (pick X priority selector). It clearly isn't well suited for
an academic publication, but it seems interesting and useful enough to
be worth sharing with a larger audience

Obviously, that sort of thing is pretty well trodden ground.
I suggest your (or your student's) first step should be to
find someone trustworthy who can review the implementation
confidentially, to see whether it's in fact a well known
technique - it's surprising how many of these things are
sloshing around in the tribal memory without ever surfacing
as a publication.

Then, if it's just a neat implementation of something
reasonably well known, informal publication on the web
(even by starting a blog) sounds sensible. But if it's
really novel, maybe one of the user group conferences
such as SNUG might be interested? Or at least it might
be published on one of the better-known Verilog-related
forum and info sites such as project-veripage, veripool.org,
Verification Guild, SystemVerilog User Group or whatever,
depending on the exact subject matter.
--
Jonathan Bromley

 

[Jeremy Bennett]

On Wed, 24 Feb 2010 10:28:50 -0800, Mark Brehob wrote:

Hello all,
Is there a reasonable place to publish short papers on Verilog coding or
common algorithms? Something like a user group or something else? I've
got a student who has come up with a fairly snazzy bit of Verilog code
that runs a lot faster than a naive implementation of the same algorithm
(pick X priority selector). It clearly isn't well suited for an academic
publication, but it seems interesting and useful enough to be worth
sharing with a larger audience (and ideally go somewhere on his resume
as an actual publication rather than a newsgroup post).

Hi Mark,

Have you considered putting it on OpenCores (www.opencores.org). If your
student is happy with open sourcing his work, it will give it wide
publicity, a community willing to consider it, and an online presence
that can be referred to.


Jeremy

 

[Mark Brehob]

On Feb 24, 5:34 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

On Wed, 24 Feb 2010 10:28:50 -0800 (PST), Mark Brehob wrote:
Is there a reasonable place to publish short papers on Verilog coding
or common algorithms?  Something like a user group or something else?
I've got a student who has come up with a fairly snazzy bit of Verilog
code that runs a lot faster than a naive implementation of the same
algorithm (pick X priority selector). It clearly isn't well suited for
an academic publication, but it seems interesting and useful enough to
be worth sharing with a larger audience

Obviously, that sort of thing is pretty well trodden ground.
I suggest your (or your student's) first step should be to
find someone trustworthy who can review the implementation
confidentially, to see whether it's in fact a well known
technique - it's surprising how many of these things are
sloshing around in the tribal memory without ever surfacing
as a publication.

Then, if it's just a neat implementation of something
reasonably well known, informal publication on the web
(even by starting a blog) sounds sensible.  But if it's
really novel, maybe one of the user group conferences
such as SNUG might be interested?  Or at least it might
be published on one of the better-known Verilog-related
forum and info sites such as project-veripage, veripool.org,
Verification Guild, SystemVerilog User Group or whatever,
depending on the exact subject matter.
--
Jonathan Bromley

Thanks!

I've no doubt it is well-covered ground. Part of our problem was that
we couldn't find anyone around here who knew how to make a solid
implementation and we've needed one a number of times. One student
came up with a really nice bit of code and I figured it might be worth
sharing. Any chance you'd be willing to look at it and tell us if
it's actually interesting?

Mark