Verilog, PSL or SystemVerilog of OVL?

[Davy]

Hi all,

I am a Verilog user.
I want to use assertion based verification in my project. And I found
OVL(Open Verification library).

Do you think which one of the OVL is better? Verilog, PSL or
SystemVerilog?

And I heard SystemVerilog have the ABV feature? Why OVL supply ABV in
SystemVerilog again?

Best regards,
Davy

 

[ngsayjoe@gmail.com]

I'd recommend you to go for SystemVerilog, as it's the hardware
language of the future.

Joe,
LogicSim - Your Personal Verilog Simulator
http://www.logicsim.com

Davy wrote:

Hi all,

I am a Verilog user.
I want to use assertion based verification in my project. And I found
OVL(Open Verification library).

Do you think which one of the OVL is better? Verilog, PSL or
SystemVerilog?

And I heard SystemVerilog have the ABV feature? Why OVL supply ABV in
SystemVerilog again?

Best regards,
Davy

 

[anupam]

hi,
I recommend system verilog .its more powerful and therefore a little
hard to learn.
With system verilog you can write your own assertions better than the
predefined ones.
PSL is almost same as System Verilog Assertions

regards,
Amupam Jain