Verilog primitives vs dataflow modeling

[logic_guy]

Suppose I have a large Verilog design that is already coded at the gate
level (a netlist). Would I typically get better simulation performance
if the gates were coded like this:
assign net3 = net1 & net2;

or instantiated primitives like this:
and u1(net2, net1, net2);

I know I could devise an experiment and try it; but, could save myself
some times if others have already experimented along these lines. At
this point, I'm interested in strictly functional verification, not
delay modeling.

Thanks,
Charles Bailey

 

[Cary R.]

On 7/4/2011 10:27 AM, logic_guy wrote:

Suppose I have a large Verilog design that is already coded at the gate
level (a netlist). Would I typically get better simulation performance
if the gates were coded like this:
assign net3 = net1& net2;

or instantiated primitives like this:
and u1(net2, net1, net2);

I know I could devise an experiment and try it; but, could save myself
some times if others have already experimented along these lines. At
this point, I'm interested in strictly functional verification, not
delay modeling.

This is likely compiler/version dependent so I think you are going to
have to do the work to get an acceptable answer. If we were to speculate
we would need to know which simulator/version you are planning to use.

Cary