Verilog preprocessor macro syntax

[currentsource]

I'm trying to define a macro for a simple two-flop synchronizer in an IS
project:

`define XCLK_SYNC_2DFF(q, d, clk) \
reg __sync__``q; \
always @(posedge clk) \
begin \
__sync__``q <= d; \
q <= __sync__``q; \
end \

XST errors out on this; I believe the `` is SystemVerilog syntax which XS
doest not support. But the following doesn't work either:

`define XCLK_SYNC_2DFF(q, d, clk) \
reg sync; \
always @(posedge clk) \
begin \
sync <= d; \
q <= sync; \
end \


Limited though the utility of such a macro may be, shouldn't th
preprocessor just dump the lines above, substituting for q, d and cl
wherever it sees a `XCLK_SYNC_2DFF invocation in the source? Doe
Verilog-2001 specifically forbid creation of temp regs/wires within macros


Is there any way to code this macro while keeping XST happy? Or should
just create a separate module/inline the code?




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[Jonathan Bromley]

On Wed, 24 Nov 2010 13:50:39 -0600, "currentsource" wrote:

I'm trying to define a macro for a simple
two-flop synchronizer in an ISE project:

`define XCLK_SYNC_2DFF(q, d, clk) \
reg __sync__``q; \
always @(posedge clk) \
begin \
__sync__``q <= d; \
q <= __sync__``q; \
end \

XST errors out on this; I believe
the `` is SystemVerilog syntax

Right, it's the "token gluing" operator as you've seen.

But the following doesn't work either:

`define XCLK_SYNC_2DFF(q, d, clk) \
reg sync; \
always @(posedge clk) \
begin \
sync <= d; \
q <= sync; \
end \

Really? I can easily imagine that it will fail to compile
if you use the macro more than once in the same scope,
because it will create more than one "reg sync". But
a single use of it should be OK - provided you DON'T
put a semicolon on the end of the macro invocation.

Surely it would be easier just to make a module?
That's what they're for, after all. The extra layer
of hierarchy is completely free in hardware, and has
a negligible impact on simulation performance. And it
saves all the macro kruft.

Jonathan Bromley