Verilog parser again !

[Olivier FAURAX]

Hello,

I know this is a recurrent question, but I haven't found what I look for.

Is there a free Verilog parser/analyzer that can generate data
structures in any language ?

Verilog-Perl ( http://search.cpan.org/~wsnyder/Verilog-Perl/ ) is quite
what i need, but it lacks a feature for me
(Net->module_or_pins_connected_to_this_net).

Before trying to modify this Perl library, I want to know if there isn't
other tool that can do this work.
All languages are welcome (c++, perl, ocaml, ...).

Have a nice day.
Olivier FAURAX

 

[Charles]

I start to write a parser for "synthesizable verilog" codes with Haskell two
weeks ago. It's output is now AST (abstract syntax tree). Right now I'm
dealing with the annoying problem of expression parsing. But for most cases,
expression is not the most important thing we need, and it should be much
more easier to build a "lite parser" whose job is only extracting out net
and module informations, discarding the annoying expressions. I'm wondering
if I should make an easier "lite parser" first or keep working on the
"strict parser".

The other problem is the output format of this parser, I think the AST is a
nice format for other programs to read, maybe the AST in XML format? XML
parser is everywhere in nearly every language.

BTW, I tried verilog-perl before, I think it's more a "lexer" than a
"parser".

"Olivier FAURAX" <faurax@emse.fr.invalid> wrote in message
news:42f09279$0$15052$626a14ce@news.free.fr...

Hello,

I know this is a recurrent question, but I haven't found what I look for.

Is there a free Verilog parser/analyzer that can generate data
structures in any language ?

Verilog-Perl ( http://search.cpan.org/~wsnyder/Verilog-Perl/ ) is quite
what i need, but it lacks a feature for me
(Net->module_or_pins_connected_to_this_net).

Before trying to modify this Perl library, I want to know if there isn't
other tool that can do this work.
All languages are welcome (c++, perl, ocaml, ...).

Have a nice day.
Olivier FAURAX

 

[Petter Gustad]

Olivier FAURAX <faurax@emse.fr.invalid> writes:

Is there a free Verilog parser/analyzer that can generate data
structures in any language ?

I'll just repeat myself here:
http://groups.google.com/group/comp.lang.verilog/msg/e7a82c31d3062b1f?dmode=source&hl=en

I have made a couple Verilog parsers and I found PCCTS and ANTLR much
more intiutive and flexible than lex/yacc. There is a Verilog grammar
at:

http://www.antlr.org/grammar/verilog/verilog.g

Petter
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