Verilog or VLDL?

[dhruvin bhadani]

helooo sir,

i am intrested in VLSI as a carrer, and i dont know with what should i start, with verilog? or VLHD? and i also dont knw any computer language much , i know basic C and little bit of core JAVA, hoping for your positive response

thank you.

 

[rickman]

On 6/4/2014 5:06 PM, dhruvin bhadani wrote:

helooo sir,

i am intrested in VLSI as a carrer, and i dont know with what should i start, with verilog? or VLHD? and i also dont knw any computer language much , i know basic C and little bit of core JAVA, hoping for your positive response

I would recommend that you be fluent in both HDLs. In particular know
how the problems and shortcomings of each language. Neither is hard to
learn, but finding the problems each one creates is not so easy. VHDL
has a steeper learning curve, but I think Verilog is harder to learn
it's issues.

I'm cross posting so you can get feedback from both groups. I hope all
replies are to this branch of the thread.

--

Rick

 

[Kim Enkovaara]

On 5.6.2014 3:58, rickman wrote:

On 6/4/2014 5:06 PM, dhruvin bhadani wrote:
helooo sir,

i am intrested in VLSI as a carrer, and i dont know with what should i
start, with verilog? or VLHD? and i also dont knw any computer
language much , i know basic C and little bit of core JAVA, hoping for
your positive response

I would recommend that you be fluent in both HDLs. In particular know
how the problems and shortcomings of each language. Neither is hard to
learn, but finding the problems each one creates is not so easy. VHDL
has a steeper learning curve, but I think Verilog is harder to learn
it's issues.

I'm cross posting so you can get feedback from both groups. I hope all
replies are to this branch of the thread.

I agree that both languages are important. I have not seen for a long
time design that would not have both languages (verilog/sv + vhdl)
but I'm on the Europe side of the pond

The language is quite minor part of the design, more important is to
understand what logic the RTL generates. For real ASIC stuff etc.
schematic level understanding is also quite important (getting netlist
simulations to work, metal fixes, tinkering at gate level for last
timings etc.). If you understand digital design and its principles
the language is just a way to express those ideas.

--Kim

 

[nurabha]

Well, As others said you should learn both. VHDL is more cleaner language and Verilog more easier to follow.

I would suggest you to pick up the book "Digital Design and Computer Architecture, Second Edition [Paperback]" by David Harris, Sarah Harris. It treats both VHDL and SystemVerilog.

And yes, ultimately focus should be on understanding how to create RTL design. HDL languages are just a tool to describe your RTL. HDL languages are not software programming language like C or Java. At best they are designed to express natural concurrency in circuits. For understanding how RTL is different from Behavioral(C, Java), please read RTL VHDL book Pong Chu.

Start with creating RTL schematic of circuit on paper, write HDL to describe it, synthesize the HDL code and see if the generated RTL schematic tallies with your paper schematic.

Of course RTL level simulations and Gate level simulations(after technology mapping) should also match.

 

[Russell Merrick]

On Wednesday, June 4, 2014 5:06:12 PM UTC-4, dhruvin bhadani wrote:

helooo sir,



i am intrested in VLSI as a carrer, and i dont know with what should i start, with verilog? or VLHD? and i also dont knw any computer language much , i know basic C and little bit of core JAVA, hoping for your positive response



thank you.

I agree with others above, both are important to learn. If you're going to focus on one to start with, I would probably recommend Verilog if you're in the US and VHDL if you're in Europe. If you're elsewhere, well find out what companies near you are using and learn that language.

If you want a good reference to start learning online, check out the tutorials at http://www.nandland.com. Good luck!