B
Bill82
Guest
Hi,
I have a little problem with the verilog-mixed simulation, is it possible
to modify the logic level with some declaration in the code? I have seen
that in the SpectreVerilog simulation the logic level of the gates are 5V,
Is it possible to modify this value? thanks I'm waiting an answer!!
I have a little problem with the verilog-mixed simulation, is it possible
to modify the logic level with some declaration in the code? I have seen
that in the SpectreVerilog simulation the logic level of the gates are 5V,
Is it possible to modify this value? thanks I'm waiting an answer!!