Verilog operator

[bir]

Is "->" any kind of Verilog operator? Can anyone tell me what will the
following code do?

always @(posedge clk)
begin
if(slect1) ->rready_asserted;
if(slect2) ->wready_asserted;
end



Thanks
Bir

 

[johnp]

The -> operator triggers an event. It is useful for simulation, not
synthesis. For example:

event foo;

always @(foo)
$display("go my event");

initial
begin
#10;
->foo;
#10;
->foo;
end

Hope this helps!

John Providenza

bir wrote:

Is "->" any kind of Verilog operator? Can anyone tell me what will the
following code do?

always @(posedge clk)
begin
if(slect1) ->rready_asserted;
if(slect2) ->wready_asserted;
end



Thanks
Bir