Verilog Newbie Question

K

Kate Smith

Guest
The following code is my first Verilog program. It's running at 25MHz and
that's what the counter is for. I'm trying to accomplish the same thing by
shifting bits instead of hard coding the output in case statements. I tried
LED<=LED>>1 to no avail. Any comments and suggestions are appreciated!

Thanks!
Kate

module ledbounce(clk, LED);
input clk;
output [3:0] LED;

reg [19:0] cnt1;
reg [2:0] cnt2;
reg a, b, c, d;
wire cnt1max = (cnt1==1000000);

always @(posedge clk)
if(cnt1max)
cnt1 <= 0;
else
cnt1 <= cnt1 +1;

always @(posedge clk)
if(cnt1max)
begin
if(cnt2==5)
cnt2<=0;
else
cnt2<=cnt2+1;
end

always @(posedge clk)
begin
case(cnt2)
0 : begin
a = 1;
b = 0;
c = 0;
d = 0;
end
1 : begin
a = 0;
b = 1;
c = 0;
d = 0;
end
2 : begin
a = 0;
b = 0;
c = 1;
d = 0;
end
3 : begin
a = 0;
b = 0;
c = 0;
d = 1;
end
4 : begin
a = 0;
b = 0;
c = 1;
d = 0;
end
5 : begin
a = 0;
b = 1;
c = 0;
d = 0;
end
endcase
end

assign LED[0] = a;
assign LED[1] = b;
assign LED[2] = c;
assign LED[3] = d;

endmodule
 
"Kate Smith" <lsdjf@dlfjc.om> wrote in message
news:bNidnZqo8vXL4KbdRVn-uQ@comcast.com...
The following code is my first Verilog program. It's running at 25MHz and
that's what the counter is for. I'm trying to accomplish the same thing
by
shifting bits instead of hard coding the output in case statements. I
tried
LED<=LED>>1 to no avail. Any comments and suggestions are appreciated!

module ledbounce(clk, LED);
input clk;
output [3:0] LED;

reg [19:0] cnt1;
reg [2:0] cnt2;
reg a, b, c, d;
wire cnt1max = (cnt1==1000000);
Click to expand...
[snip code]

First, it's worth noting that you are more likely to get an
answer on comp.lang.verilog than here - although many of us
read both groups.

Second, you can't manipulate output LED as you tried, because
it's a wire, not a reg - you declared it correctly as an
output, but outputs are wires by default. You need to do the
shift operations on the register you've represented as
a,b,c,d.

Third, although I can see the sense in your counter arrangement,
the second counter is not really necessary - you could use the
"bouncing bit" 4-bit register as its own counter.

Fourth, you REALLY need to think about reset strategy -
in many FPGA and CPLD devices, flip-flops start life with
zero in them, but it's a bad idea to rely on this.

So, here's my suggestion:

(1) Throw away your cnt2 logic and registers a,b,c,d.
(2) Make the bouncing-bit counter like this:

reg LeftNotRight;
reg [3:0] LED; // This in addition to the output declaration
....
always @(posedge clk or posedge reset)
if (reset) begin
LED <= 1;
LeftNotRight <= 1;
end else if (cnt1max) begin
if (LeftNotRight) begin // Going left
if (LED[3])
LeftNotRight <= 0;
else
LED <= LED << 1;
end else begin // Going right
if (LED[0])
LeftNotRight <= 1;
else
LED <= LED >> 1;
end
end

For lots of extra credit, see if you can work out
a) what happens if the LED register gets more than
one of its bits set, for any reason;
b) what happens if the LED register becomes zero
for any reason, and what you might do to fix it

:)

--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Second, you can't manipulate output LED as you tried, because
it's a wire, not a reg - you declared it correctly as an
output, but outputs are wires by default. You need to do the
shift operations on the register you've represented as
a,b,c,d.
Click to expand...
I don't see why what she's done wouldn't work. Her registers a,b,c, and d
change at the clock edge and the LED wires are connected to the outputs of
the registers.

The only problem I might see is that it runs a bit fast. The "state
machine" changes states at 25Hz and it might be hard to see the LEDs blink
that quickly.

-Kevin
 
"Kevin Neilson" <kevin_neilson@removethiscomcast.net>
wrote in message news:ZSL_b.5237$AL.131989@attbi_s03...

I don't see why what she's done wouldn't work. Her registers a,b,c, and d
change at the clock edge and the LED wires are connected to the outputs of
the registers.
Click to expand...
The code as presented was fine, yes. I was talking about the
attempt to set LED <= LED >> 1, as mentioned at the start of the
original post. Sorry I didn't make that clear.

--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
BEAUTIFUL!!!
Thanks Jonathan! This is exactly what I was looking for! I appreciate your
response! I'll move my further discussions to comp.lang.verilog.

Thanks again!
Kate

"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message
news:c1g15b$8rt$1$8302bc10@news.demon.co.uk...
"Kate Smith" <lsdjf@dlfjc.om> wrote in message
news:bNidnZqo8vXL4KbdRVn-uQ@comcast.com...
The following code is my first Verilog program. It's running at 25MHz
and
that's what the counter is for. I'm trying to accomplish the same thing
by
shifting bits instead of hard coding the output in case statements. I
tried
LED<=LED>>1 to no avail. Any comments and suggestions are appreciated!

module ledbounce(clk, LED);
input clk;
output [3:0] LED;

reg [19:0] cnt1;
reg [2:0] cnt2;
reg a, b, c, d;
wire cnt1max = (cnt1==1000000);

[snip code]

First, it's worth noting that you are more likely to get an
answer on comp.lang.verilog than here - although many of us
read both groups.

Second, you can't manipulate output LED as you tried, because
it's a wire, not a reg - you declared it correctly as an
output, but outputs are wires by default. You need to do the
shift operations on the register you've represented as
a,b,c,d.

Third, although I can see the sense in your counter arrangement,
the second counter is not really necessary - you could use the
"bouncing bit" 4-bit register as its own counter.

Fourth, you REALLY need to think about reset strategy -
in many FPGA and CPLD devices, flip-flops start life with
zero in them, but it's a bad idea to rely on this.

So, here's my suggestion:

(1) Throw away your cnt2 logic and registers a,b,c,d.
(2) Make the bouncing-bit counter like this:

reg LeftNotRight;
reg [3:0] LED; // This in addition to the output declaration
...
always @(posedge clk or posedge reset)
if (reset) begin
LED <= 1;
LeftNotRight <= 1;
end else if (cnt1max) begin
if (LeftNotRight) begin // Going left
if (LED[3])
LeftNotRight <= 0;
else
LED <= LED << 1;
end else begin // Going right
if (LED[0])
LeftNotRight <= 1;
else
LED <= LED >> 1;
end
end

For lots of extra credit, see if you can work out
a) what happens if the LED register gets more than
one of its bits set, for any reason;
b) what happens if the LED register becomes zero
for any reason, and what you might do to fix it

:)

--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW,
UK
Tel: +44 (0)1425 471223 mail:
jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
 
Thanks much Jonathan!!! Worked like a charm!!! I'll move all further
discussions to comp.lang.verilog

Thanks again!


"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message
news:c1g15b$8rt$1$8302bc10@news.demon.co.uk...
"Kate Smith" <lsdjf@dlfjc.om> wrote in message
news:bNidnZqo8vXL4KbdRVn-uQ@comcast.com...
The following code is my first Verilog program. It's running at 25MHz
and
that's what the counter is for. I'm trying to accomplish the same thing
by
shifting bits instead of hard coding the output in case statements. I
tried
LED<=LED>>1 to no avail. Any comments and suggestions are appreciated!

module ledbounce(clk, LED);
input clk;
output [3:0] LED;

reg [19:0] cnt1;
reg [2:0] cnt2;
reg a, b, c, d;
wire cnt1max = (cnt1==1000000);

[snip code]

First, it's worth noting that you are more likely to get an
answer on comp.lang.verilog than here - although many of us
read both groups.

Second, you can't manipulate output LED as you tried, because
it's a wire, not a reg - you declared it correctly as an
output, but outputs are wires by default. You need to do the
shift operations on the register you've represented as
a,b,c,d.

Third, although I can see the sense in your counter arrangement,
the second counter is not really necessary - you could use the
"bouncing bit" 4-bit register as its own counter.

Fourth, you REALLY need to think about reset strategy -
in many FPGA and CPLD devices, flip-flops start life with
zero in them, but it's a bad idea to rely on this.

So, here's my suggestion:

(1) Throw away your cnt2 logic and registers a,b,c,d.
(2) Make the bouncing-bit counter like this:

reg LeftNotRight;
reg [3:0] LED; // This in addition to the output declaration
...
always @(posedge clk or posedge reset)
if (reset) begin
LED <= 1;
LeftNotRight <= 1;
end else if (cnt1max) begin
if (LeftNotRight) begin // Going left
if (LED[3])
LeftNotRight <= 0;
else
LED <= LED << 1;
end else begin // Going right
if (LED[0])
LeftNotRight <= 1;
else
LED <= LED >> 1;
end
end

For lots of extra credit, see if you can work out
a) what happens if the LED register gets more than
one of its bits set, for any reason;
b) what happens if the LED register becomes zero
for any reason, and what you might do to fix it

:)

--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW,
UK
Tel: +44 (0)1425 471223 mail:
jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
 
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