Verilog newbie question

L

lei

Guest
Hi All:
I just started learning Verilog, I am using xilinx ISE 9.2i for my
development. The following is a piece of code that I copied mostly
(from fpga4fun).

module led(clk_in, clk_out, data_in);
input clk_in;
output clk_out;
input [12:0] data_in;

reg clk_out;

parameter INPUT_CLK = 50000000; //input clock is 50mhz
parameter OUTPUT_CLK = 60; //60hz to refresh the LED.
parameter CLK_ACC_INC_WIDTH = 20; //Use 20 bit accumulater.
parameter CLK_ACC_INC = (OUTPUT_CLK << CLK_ACC_INC_WIDTH) /
INPUT_CLK;

reg [CLK_ACC_INC_WIDTH:0] clk_acc;

initial
begin
clk_acc = 0;
clk_out = 0;
end

always @(posedge clk_in)
begin
clk_acc = clk_acc[19:0] + CLK_ACC_INC;
clk_out = clk_acc[20];
end
endmodule

The code passed synthesis step, but after i created test bench
waveform and run the simulation, it either:
1. clk_in is Z, so everything is straight line, basically means no
clock .
2. clk_in appears to be right, but the clk_acc is not being
accumulated.

Can anybody shed some lights on me ? what is going on with ISE? why
clk_in is not being driven?
I've been trying various step for 2 days , and can't figure out what's
the problem.
Appreciate your help.

Thank you!
lei
 
lei wrote:
Hi All:
I just started learning Verilog, I am using xilinx ISE 9.2i for my
development. The following is a piece of code that I copied mostly
(from fpga4fun).

module led(clk_in, clk_out, data_in);
input clk_in;
output clk_out;
input [12:0] data_in;

reg clk_out;

parameter INPUT_CLK = 50000000; //input clock is 50mhz
parameter OUTPUT_CLK = 60; //60hz to refresh the LED.
[...]

The code passed synthesis step, but after i created test bench
waveform and run the simulation, it either:
Click to expand...
You should do the simulation first. Passing synthesis only means the
code is synthesizable. No meaning about functionality. Could be that
synthesis did optimize all your logic away.

1. clk_in is Z, so everything is straight line, basically means no
clock .
2. clk_in appears to be right, but the clk_acc is not being
accumulated.
Click to expand...
Hard to tell without seeing the test bench. But just a comment about the
module, based on the code you provided. The input clock is 50MHz and the
LED refresh rate is 60Hz. Just think about that timing difference and
think about how long you have to simulate in order to see an output.

Cheers,

Guenter
 
On Sun, 25 May 2008 22:43:49 -0700 (PDT), lei <leisun124@gmail.com>
wrote:
<snip>
always @(posedge clk_in)
begin
clk_acc = clk_acc[19:0] + CLK_ACC_INC;
clk_out = clk_acc[20];
end
endmodule

The code passed synthesis step,
Click to expand...
It seeems to be an attempt to get 60Hz clock from 50MHz input; the
CLK_ACC_INC is calculated to get such a result.

I suspect you didn't look at the warnings.

They tell you that data_in isn't used, and that clk_acc[20] isn't
assigned.

clk_acc = clk_acc[19:0] + CLK_ACC_INC;

increments clk_acc[19:0], but leaves clk_acc[20] unchanged.

A 20-wide accumulator is actually

reg [19:0] clk_acc;

CLK_ACC_INC_WIDTH is specified as 20, and yet the number "20" is used
instead of this parameter in the code. Why not use the parameter
rather than the number?

The following works:

####################

module led(clk_in, clk_out);
input clk_in;
output clk_out;

reg clk_out;

parameter INPUT_CLK = 50000000; //input clock is 50MHz
parameter OUTPUT_CLK = 60; //60Hz to refresh
the LED.
parameter CLK_ACC_INC_WIDTH = 24; //Use 24 bit accumulator.
parameter CLK_ACC_INC = (OUTPUT_CLK << CLK_ACC_INC_WIDTH) /
INPUT_CLK;

reg [CLK_ACC_INC_WIDTH-1:0] clk_acc;

initial
begin
clk_acc = 0;
clk_out = 0;
end

always @(posedge clk_in)
begin
clk_acc = clk_acc[CLK_ACC_INC_WIDTH-1:0] +
CLK_ACC_INC;
clk_out = clk_acc[CLK_ACC_INC_WIDTH-1];
end

endmodule
#############

Note that I've changed CLK_ACC_INC_WIDTH to 24. If you leave it at 20,
CLK_ACC_INC is 1.258. It gets truncated to 1, and clk_acc just counts
up. CLK_ACC_INC_WIDTH = 24 gives CLK_ACC_INC=20.132, truncated to 20,
and so the accumulator overflows (irregularly) at a 60Hz rate. A
longer accumulator would give a less irregular output.

As Guenter says, do think about how long you'll have to run the sim to
see output changes.
--
Only three people have ever understood the Schleswig-Holstein problem
One's dead, one's gone mad, and I've forgotten.
 
On May 26, 1:49 am, Guenter Dannoritzer <kratfkryk...@spammotel.com>
wrote:

Hard to tell without seeing the test bench. But just a comment about the
module, based on the code you provided. The input clock is 50MHz and the
LED refresh rate is 60Hz. Just think about that timing difference and
think about how long you have to simulate in order to see an output.

Cheers,

Guenter
Click to expand...
Hi Guenter:
Thanks for the comment.
I did figured out the simulation is 1000ns, so due to the frequency
difference, i may not able to see the output clock changing, but i
should be able to see the clk_acc is accumulating in each posedege of
the clock, but I didn't, at time 1000ns, the last value of clk_acc is
still 0.
 
On May 26, 2:43 am, tersono <ethel.thef...@ntlworld.com> wrote:
On Sun, 25 May 2008 22:43:49 -0700 (PDT), lei <leisun...@gmail.com
wrote:
snip



always @(posedge clk_in)
begin
clk_acc = clk_acc[19:0] + CLK_ACC_INC;
clk_out = clk_acc[20];
end
endmodule

The code passed synthesis step,

It seeems to be an attempt to get 60Hz clock from 50MHz input; the
CLK_ACC_INC is calculated to get such a result.

I suspect you didn't look at the warnings.

They tell you that data_in isn't used, and that clk_acc[20] isn't
assigned.

clk_acc = clk_acc[19:0] + CLK_ACC_INC;

increments clk_acc[19:0], but leaves clk_acc[20] unchanged.

A 20-wide accumulator is actually

reg [19:0] clk_acc;

CLK_ACC_INC_WIDTH is specified as 20, and yet the number "20" is used
instead of this parameter in the code. Why not use the parameter
rather than the number?

The following works:

####################

module led(clk_in, clk_out);
input clk_in;
output clk_out;

reg clk_out;

parameter INPUT_CLK = 50000000; //input clock is 50MHz
parameter OUTPUT_CLK = 60; //60Hz to refresh
the LED.
parameter CLK_ACC_INC_WIDTH = 24; //Use 24 bit accumulator.
parameter CLK_ACC_INC = (OUTPUT_CLK << CLK_ACC_INC_WIDTH) /
INPUT_CLK;

reg [CLK_ACC_INC_WIDTH-1:0] clk_acc;

initial
begin
clk_acc = 0;
clk_out = 0;
end

always @(posedge clk_in)
begin
clk_acc = clk_acc[CLK_ACC_INC_WIDTH-1:0] +
CLK_ACC_INC;
clk_out = clk_acc[CLK_ACC_INC_WIDTH-1];
end

endmodule
#############

Note that I've changed CLK_ACC_INC_WIDTH to 24. If you leave it at 20,
CLK_ACC_INC is 1.258. It gets truncated to 1, and clk_acc just counts
up. CLK_ACC_INC_WIDTH = 24 gives CLK_ACC_INC=20.132, truncated to 20,
and so the accumulator overflows (irregularly) at a 60Hz rate. A
longer accumulator would give a less irregular output.

As Guenter says, do think about how long you'll have to run the sim to
see output changes.
--
Only three people have ever understood the Schleswig-Holstein problem
One's dead, one's gone mad, and I've forgotten.
Click to expand...
Hi tersono:
Thank you very much for your inputs! It's right that using 24 bit
accumulator, I should get 60hz from 50mhz input clock. However, my
simulation still fail, basically, the input clock is "Z", I guess it
would be hard to tell what the problem is, I've uploaded my project
(about 379K zipped file) into:
http://www.MegaShare.com/418855
I am starting to wonder if my ISE got problem or not. I appreciate
if anyone can download the project and run a sim. see if it behave
differently on your machine.
Thank you!

Regards
lei
 
On Mon, 26 May 2008 15:28:24 -0700 (PDT), lei <leisun124@gmail.com>
wrote:
<snip>
I've uploaded my project
(about 379K zipped file) into:
http://www.MegaShare.com/418855
I am starting to wonder if my ISE got problem or not. I appreciate
if anyone can download the project and run a sim. see if it behave
differently on your machine.
Thank you!

Regards
lei
Click to expand...
Unfortunately I can't see the file- or I'm being dumb about how to
drive it.

Here's my stimulus file, tf1.v :
##################
module tf1_v;

// Inputs
reg clk_in;


// Outputs
wire clk_out;

// Instantiate the Unit Under Test (UUT)
led uut (
.clk_in(clk_in),
.clk_out(clk_out)
);

initial begin
// Initialize Inputs
clk_in = 0;


// Wait 100 ns for global reset to finish
#100;

// Add stimulus here

end

always #5 clk_in=!clk_in;

always
begin
#40000000 $stop;
end

endmodule
#################
- see if that helps.
If it doesn't, send me the .zip at this address and I'll have a look
at it.
I do *not* claim to have all the answers!
--
Only three people have ever understood the Schleswig-Holstein problem
One's dead, one's gone mad, and I've forgotten.
 
If your input clk is "z" .. would not the solution be to add a stimulus to
your testbench to get that to "wiggle"? Usually not much happens in a
synchronous design if there is no clock.

Mike
Click to expand...
When I opened my testbench, the waveform looks corrrect. But after
running simulation, the input clock showed up as Z, a straight line! I
don't know why this happened.
 
On Tue, 27 May 2008 11:19:39 -0700 (PDT), lei <leisun124@gmail.com>
wrote:

If your input clk is "z" .. would not the solution be to add a stimulus to
your testbench to get that to "wiggle"? Usually not much happens in a
synchronous design if there is no clock.

Mike

When I opened my testbench, the waveform looks corrrect. But after
running simulation, the input clock showed up as Z, a straight line! I
don't know why this happened.
Click to expand...
I wonder...

In the drop-down list at top left, you've selected "behavioural
simulation"- I'm sure you've done that.

In the upper of the two panes on the left, you must highlight the
*stimulus* file, not the design file, before starting the simulator in
the lower left pane.

Have you perhaps highlighted the design file instead?
--
Only three people have ever understood the Schleswig-Holstein problem
One's dead, one's gone mad, and I've forgotten.
 
On May 27, 10:06 pm, tersono <ethel.thef...@ntlworld.com> wrote:
On Tue, 27 May 2008 11:19:39 -0700 (PDT), lei <leisun...@gmail.com
wrote:



If your input clk is "z" .. would not the solution be to add a stimulus to
your testbench to get that to "wiggle"? Usually not much happens in a
synchronous design if there is no clock.

Mike

When I opened my testbench, the waveform looks corrrect. But after
running simulation, the input clock showed up as Z, a straight line! I
don't know why this happened.

I wonder...

In the drop-down list at top left, you've selected "behavioural
simulation"- I'm sure you've done that.

In the upper of the two panes on the left, you must highlight the
*stimulus* file, not the design file, before starting the simulator in
the lower left pane.

Have you perhaps highlighted the design file instead?
--
Only three people have ever understood the Schleswig-Holstein problem
One's dead, one's gone mad, and I've forgotten.
Click to expand...
Oh, YES!!
Thanks for pointing that out! I highlighted the UUT instead.
Thank you so much for helping out here, a simple mistake which cost me
4 days!

Again, appreciate your help! This topic is closed!

Regards
lei
 
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