verilog newbie and XST error

[James Fitzsimons]

Hi all,
thanks with your help on that last problem. I am making progress!

I am now trying to use XST to do the synthesis, but am getting the
following error:

========================================================================
=
* HDL Analysis *
========================================================================
=
Analysis of file <counter.v> succeeded.


Analyzing module <counter>.
ERROR:Xst:899 - counter.v line 23: The logic for <out> does not match a
known FF or Latch template.

Found 1 error(s). Aborting synthesis.
CPU : 0.28 / 3.51 s | Elapsed : 1.00 / 6.00 s

-->


My modified verilog is below. If anyone could shed some light on what's
going on I'd be most appreciative.

Also can someone point me to a place where I might find the part names I
should be using in my XST script? I have looked in the XST users manual,
but it doesn't really provide any help. At the moment for the XC9536
device I am using xc9536-5pc44...

Thanks very much,
James Fitzsimons


module counter(out, clk, reset);

parameter WIDTH = 8;

output [WIDTH-1 : 0] out;
input clk, reset;

reg [3 : 0] count;
reg [WIDTH-1 : 0] out;
wire clk, reset;

always @(posedge clk or posedge reset)
begin
if (reset) // Asynchrous reset
count <= 0;
else if (count < 9)
count <= count + 1;
else
count <= 0;

// now that we have a value for count, we need to convert
// that to a real 8 bit output to drive the display
case (count)
0 : out = 8'b00111111;
1 : out = 8'b00110000;
2 : out = 8'b01101101;
3 : out = 8'b01111001;
4 : out = 8'b01110010;
5 : out = 8'b01011011;
6 : out = 8'b01011110;
7 : out = 8'b00110001;
8 : out = 8'b01111111;
9 : out = 8'b01111011;
default: out = 8'b00000000;
endcase
end


endmodule // counter

module test;

reg reset;
reg clk;
wire [7:0] value;
counter c1 (value, clk, reset);

/* Make a reset that pulses once. */
initial begin
reset = 0;
clk = 0;
#17 reset = 1;
#11 reset = 0;
#29 reset = 1;
#11 reset = 0;
#160 $finish;
end

/* Make a regular pulsing clock. */
always #5 clk = !clk;

initial $monitor("At time %t, value = %b", $time, value);

endmodule // test

 

[Jonathan Bromley]

"James Fitzsimons" <jamesfit@nospam.paradise.net.nz> wrote in
message news:20030901233122890+1200@news.paradise.net.nz...

ERROR:Xst:899 - counter.v line 23: The logic for <out> does not match a
known FF or Latch template.

The error is caused because you didn't assign to "out" in the
reset branch of the process. When you write a clocked process
with reset, every signal that's assigned-to at all MUST be
assigned in both the reset branch and the clocked branch,
even though you and I know that you don't really need to
reset it. To find out why in gory detail, come on our
Expert Verilog course

By the way: are you happy that signal "out" is also registered,
so that it lags the counter by one clock cycle? If so, then
what you've done is fine - you have created a pipeline
register on the output decoder. But if (as I guess) you just
want decoding logic, you should move all the "out" logic to
a separate always block that represents the combinational
decoder:

always @(posedge clock or posedge reset)
if (reset)
count <= 0;
else
.. do your thing with "count";

always @(count)
case (count)
... make your decoder to drive "out"
endcase

HTH
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[James Fitzsimons]

Hi Jonathan,
thanks very much for your help!

By the way: are you happy that signal "out" is also registered,
so that it lags the counter by one clock cycle? If so, then
what you've done is fine - you have created a pipeline
register on the output decoder. But if (as I guess) you just
want decoding logic, you should move all the "out" logic to
a separate always block that represents the combinational
decoder:

You were spot on with that guess. I wasn't sure why the output lagged by one
clock cycle in my simulations.
I modified my code as you suggested and this actually fixed the original
error that XST was giving me.

ERROR:Xst:899 - counter.v line 23: The logic for <out> does not match a
known FF or Latch template.

The error is caused because you didn't assign to "out" in the
reset branch of the process. When you write a clocked process
with reset, every signal that's assigned-to at all MUST be
assigned in both the reset branch and the clocked branch,
even though you and I know that you don't really need to
reset it.

So, since putting my decoding logic into its own always block resolved the
problem, do I still need to do this? If so, would I just do something like
"out <= 0;" ?

To find out why in gory detail, come on our
Expert Verilog course

I would love to, but it could be a little difficult from New Zealand ;-) Can
you recommend any online resources or books I might be able to read to
better my understanding of this stuff?

Cheers,
James Fitzsimons

 

[Jonathan Bromley]

"James Fitzsimons" <jamesf@nospam.intergen.co.nz> wrote in
message news:3f53d6c4$1@news.iconz.co.nz...

I modified my code as you suggested and this actually fixed the original
error that XST was giving me.

Yes, because "out" is no longer assigned inside the clocked process.
Therefore, it isn't subject to the "clocked template" constraints.

So, since putting my decoding logic into its own always block resolved the
problem, do I still need to do this? If so, would I just do something like
"out <= 0;" ?

"out" isn't a flip-flop, therefore it doesn't need resetting

However, you've touched on an interesting point. Consider the always
block and case statement that implement your decoder on "out":

always @(count) begin
case (count)
0: out = 7'b......;
...
endcase
end

This kind of process (always block) describes purely combinational
logic, with no feedback from outputs to inputs. But suppose for
a moment that you had skipped the "default:" branch of the case.
(You didn't, and so you didn't suffer this problem....) The
overall effect of missing the default would be to insert this:
default: out = out; // don't change the output
This, of course, represents asynchronous feedback around the
logic. Bad, bad, bad. An alternative way to fix it is to make
a default assignment to the output:

always @(count) begin
out <= 0;
case (count)
... // some cases not covered
endcase
end

Because of the default assignment, the output is given a value
every time the process is triggered, and everything is OK.

I would love to, but it could be a little difficult from New Zealand ;-)
Can
you recommend any online resources or books I might be able to read to
better my understanding of this stuff?

The world of Verilog synthesis is (in my opinion) not so well served
by textbooks as the corresponding VHDL area. Dunno why.

Try to get your hands on a copy of the Verilog synthesisable-subset
standard (IEEE 1364.1), although you will have to pay for it if
you can't see it in a local or university library.

Doug Smith's book "HDL Chip Design" is quite nice, has a load of
examples, and offers all the examples in both VHDL and Verilog
so you can also see how to do it in a proper language ;->

Finally, Xilinx have stacks of appnotes about how to write
synthesisable logic (so do all the other FPGA vendors,
but I guess you're using Xilinx).

Enjoy
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.