Verilog Netlist Conversion

[Sreekumar]

Hi,

I have a verilog netlist which has some hierarchial structures in it
(for eg, a 4x1 mux built using 2x1 muxes. The 4x1 mux module has
instances of 2x1 muxes in its body and the 2x1 muxes are built using
basic gates). I would like it to be converted to a flat netlist (ie.,
it should have only one module 4x1 and everything in that should be
only basic gates). Is there any utility tools which can do this for
me?

Thanks for the help

Sreekumar