Verilog net resolution an hierarchy

[Mark Curry]

For verilog net types (I'm refering to the default "resolved" types: wire,
wor, wand, etc), the net resolution tables from the Verilog standard
define the resolution for multiply driven nets.
(Table 6-2 through 6-4) (IEEE 1800-2012).

What I'm unsure about, however, is how hierarchy plays into the net resolution.

Consider the following:

Top level module with a single net:
wor y;

sub-modules that drive (port is an output wor y):
sub1 sub1( .y( y ) );
sub2 sub2( .y( y ) );


Sub1 drives y = 0;
Sub2 drives y = 1;

If I display "y" at each level of hier,
I can see two alternatives:

Alt 1:
top y = 1
sub1 y = 0
sub2 y = 1

Alt 2:
top y = 1
sub1 y = 1
sub2 y = 1

Alt 1 would be a stricter definition of the net resolution - it happens at
a scope level. (three nets are resolved, one at each level of hierarchy).

Alt 2 would be a looser definition of port direction. Here, the net is one
net, so resolution happens once. But the resolved value travels backwards
through the output port to the sub-level 1.

Modelsim says Alt 2 is correct. Both with and without vopt. ( I'd thought
port collapsing in the optimization could change the behaviour..)

I'm curious as to anywhere in the standard I can point to say this is
unequivocally true. Will all sims / synthesis agree?

I'm actually ok with either solution, I think, as long as it's consistent.

(I've actually used WOR's a lot in my code, but never "resampled", and output
and depended on it's resolved type. I've got a situation where it may be
useful to do so)

Any comments from Verilog standards experts?

Thanks,

Mark

 

[Mark Curry]

In article <li7ejg$na1$1@dont-email.me>, Mark Curry <gtwrek@sonic.net> wrote:

For verilog net types (I'm refering to the default "resolved" types: wire,
wor, wand, etc), the net resolution tables from the Verilog standard
define the resolution for multiply driven nets.
(Table 6-2 through 6-4) (IEEE 1800-2012).

What I'm unsure about, however, is how hierarchy plays into the net
resolution.

Consider the following:

Top level module with a single net:
wor y;

sub-modules that drive (port is an output wor y):
sub1 sub1( .y( y ) );
sub2 sub2( .y( y ) );


Sub1 drives y = 0;
Sub2 drives y = 1;

If I display "y" at each level of hier,
I can see two alternatives:

Alt 1:
top y = 1
sub1 y = 0
sub2 y = 1

Alt 2:
top y = 1
sub1 y = 1
sub2 y = 1

Alt 1 would be a stricter definition of the net resolution - it happens at
a scope level. (three nets are resolved, one at each level of hierarchy).

Alt 2 would be a looser definition of port direction. Here, the net is one
net, so resolution happens once. But the resolved value travels backwards
through the output port to the sub-level 1.

Modelsim says Alt 2 is correct. Both with and without vopt. ( I'd thought
port collapsing in the optimization could change the behaviour..)

I'm curious as to anywhere in the standard I can point to say this is
unequivocally true. Will all sims / synthesis agree?

Couldn't get any Verilog standard person to answer huh?

Well, in any case, did some testcases myself.
Modelsim, as I noted above says "Alt 2" is correct. (Both with, and without
vopt)

My three synthesis tools (vivado, ise, synplify) say "Alt 1" is correct.
Interesting potential sim/synthesis mismatch there.

Digging deep into the Verilog standard, I really think
this is a complete grey area. The Sections on port collapsing,
and "inout" coercion are noteworthy, but don't give a concrete answer.

Frustrating that such an inconsistency is still within the verilog
standard soo many years later. I just needed a consistent
answer one way or the other...

--Mark