Verilog module not working,binary division,shifting problem!

[Kristo Godari]

Sorry for my poor english :/
I want to divide unsigned binary integers using non-restoring division!
I have found te algorithm here:
http://stackoverflow.com/questions/12133810/non-restoring-division-algorithm

I have implemented the algorithm on verilog.But for some reason the module does not work correct!
The module code:
I have comented where i think the mistake is!
module divider(
output reg[7:0] q,
output reg[7:0] r,
input [7:0] a, b);

reg[7:0] A;
reg[7:0] B;
reg[7:0] Q;
reg[7:0] M;
reg[7:0] N;


always @(*)
begin

A=8'b00000000;
Q=a;
M=b;
N=8;

while(N > 0)begin

if( A < 0 )
begin
A=A<<1;
Q=Q<<1;
A=A+M;
end
else
begin
//When N=8 A=00000000
A=A<<1;//I have done debugging and here does not shift A with 1 bit,it must but it doesnt why??
Q=Q<<1;
A=A-M;
end
if( A < 0 )
begin
Q[0]=0;
N=N-1;
end
else begin
Q[0]=1;
N=N-1;
end
end
if(A<0)begin
A=A+M;
end
q=Q;
r=A;

end

endmodule

Can anyone find where is my mistake?? Thank you!