Guest
Hi all,
In my design all the modules are in VHDL except one which is in
verilog.I wanted to know if it is possible to call my verilog module in
my VHDL top level.
If possible can any body tell me how to go about it.
Regards,
Praveen
In my design all the modules are in VHDL except one which is in
verilog.I wanted to know if it is possible to call my verilog module in
my VHDL top level.
If possible can any body tell me how to go about it.
Regards,
Praveen