Verilog module hierarchical references and localparam assign

D

davew

Guest
Hello,
I would like to be able to read back localparams from a module (localparams because these would be by definition read only) and assign the value to a localparam in the parent module. I have done this successfully in Modelsim using hierarchical reference and it works fine, however it doesn't appear to be supported by my Synthesis tool (Quartus in my case). Quartus complains "constant expression cannot contain a hierarchical identifier" which would seem to seal the deal.

My question is: is this allowed by the language? Looking at the IEEE Std 1800™-2012 LRM, I think it specifies that only constant literals can be assigned to localparams and parameters and I quote:
"
param_assignment ::= // from A.2.4
parameter_identifier { unpacked_dimension } [ = constant_param_expression
"

But of course reading the value of a hierarchical parameter reference e.g. a.b.param1 would resolve to either a further reference or ultimately to a constant literal (hopefully).

e.g.

module module1(...);
localparam a = minst2.a; // resolves to minst2.minst3.a value=3
module2 minst2(...);
...
end module

module module2(...);
localparam a = minst3.a;
module3 minst3(...);
...
end module

module module3(...);
localparam a = 3;
...
end module

Thank you.
 

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