verilog memory array copy

[Nahum Barnea]

Hi.

I have a very slow verilog testbench.
I used Modelsim profiler and found out that 75% of the CPU time is
consumed on a task that perform copy from one memory array to other
memory array.

Since I do not know other way, the task use a for loop over the memory
elements
and copy each one.
The task works in zero simulation time but consumes alot of CPU time.

Is there a faster way to do memory array copy using verilog-2001
features or smart PLI / systemC that linked to the simulator.

ThankX,
NAHUM.

 

[Swapnajit Mittra]

nahum_barnea@yahoo.com (Nahum Barnea) wrote in message news:<fc23bdfc.0401070717.55ff6b6e@posting.google.com>...

Hi.

I have a very slow verilog testbench.
I used Modelsim profiler and found out that 75% of the CPU time is
consumed on a task that perform copy from one memory array to other
memory array.

Since I do not know other way, the task use a for loop over the memory
elements
and copy each one.
The task works in zero simulation time but consumes alot of CPU time.

Is there a faster way to do memory array copy using verilog-2001
features or smart PLI / systemC that linked to the simulator.

ThankX,
NAHUM.

If I were you, I would check whether it is required to copy
one memory -entirely- into another. If you think of real systems,
there is hardly any example where you need to copy one memory
in its entirety to another in one clock. If you are designing
a testbench like application, I would discourage it.

Instead, I would see if I can do the job by fetching selective
locations of memory into local registers and then perform
in place calculations on them.

If this is a real design, be aware of the limitation of how
much data you can access on each clock (read port width).

You can definitely write your own PLI application to play
with the memory instance though I am unsure if that will be any
faster. See the following link as an example:

http://www.angelfire.com/ca/verilog/pli1.html

Regards
- Swapnajit.