Verilog LIF translator

S

Shamik

Guest
I need the source code for a public domain verilog parser. I am
working on a project that needs a Verilog to LIF translator. Does a
tool exist for doing that ?
 
On May 29, 3:27 pm, Shamik <shamik.gang...@gmail.com> wrote:
I need the source code for a public domain verilog parser. I am
working on a project that needs a Verilog to LIF translator. Does a
tool exist for doing that ?
Click to expand...
I'm not exactly sure what LIF is, but there are perl parsers for
Verilog. See

http://cpan.uwinnipeg.ca/dist/Hardware-Verilog-Parser

David Walker
 
On May 29, 3:27 pm, Shamik <shamik.gang...@gmail.com> wrote:
I need the source code for a public domain verilog parser. I am
working on a project that needs a Verilog to LIF translator. Does a
tool exist for doing that ?
Click to expand...
I'm not exactly sure what LIF is, but there are perl parsers for
Verilog. See

http://cpan.uwinnipeg.ca/dist/Hardware-Verilog-Parser

David Walker
 
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Shamik wrote:
I need the source code for a public domain verilog parser. I am
working on a project that needs a Verilog to LIF translator. Does a
tool exist for doing that ?
Click to expand...
One possibility is to use Icarus Verilog. You can write your
own code generator to generate any form of output from the
elaborated design.

What's "LIF"?

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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On May 30, 10:44 pm, Stephen Williams <spamt...@icarus.com> wrote:
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Shamik wrote:
I need the source code for a public domain verilog parser. I am
working on a project that needs a Verilog to LIF translator. Does a
tool exist for doing that ?

One possibility is to use Icarus Verilog. You can write your
own code generator to generate any form of output from the
elaborated design.

What's "LIF"?

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,http://www.icarus.com and lines to code before I sleep,http://www.picturel.com And lines to code before I sleep."
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Click to expand...
Thanks a lot Steve.
Would you please elaborate a bit how I can use Icarus to do the
translation from Verilog to LIF (the format's details don't matter,
actually its not a standard format and stands for List Intermediate
Format)? I mean how do I get the output after the elaboration stage so
that I can process it?
 
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Shamik wrote:

Thanks a lot Steve.
Would you please elaborate a bit how I can use Icarus to do the
translation from Verilog to LIF (the format's details don't matter,
actually its not a standard format and stands for List Intermediate
Format)? I mean how do I get the output after the elaboration stage so
that I can process it?
Click to expand...
There is some documentation for this feature here:

<http://iverilog.wikia.com/wiki/Using_Loadable_Target_API>

The idea is that the core compiler does the parse and elaboration,
including resolving libraries and doing all the yucky error handling,
then invokes a code generator to write out the checked result in
the desired form. There is a "vvp" code generator that generates
the run-time simulation, there is a "null" code generator that
does nothing and there is a "stub" code generator that I use for
debugging.

The web page above (part of the larger Icarus Verilog documentation)
should be enough to get you started with a code generator, including
installing an example. The ivl_target.h header file that comes with
Icarus Verilog defines the complete API for accessing the elaborated
design, so you can read that to get an idea how complete it is.

The purpose of this API is exactly to allow people to write
translators that take advantage of all the parsing/error checking
that the compiler already does. All you have to do is write a
function that scans the design at your leisure and does whatever
you want with it.
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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On May 29, 3:27 pm, Shamik <shamik.gang...@gmail.com> wrote:
I need the source code for a public domain verilog parser. I am
working on a project that needs a Verilog to LIF translator. Does a
tool exist for doing that ?
Click to expand...
I'm not exactly sure what LIF is, but there are perl parsers for
Verilog. See

http://cpan.uwinnipeg.ca/dist/Hardware-Verilog-Parser

David Walker
 
On May 31, 10:25 pm, Stephen Williams <spamt...@icarus.com> wrote:
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Shamikwrote:
Thanks a lot Steve.
Would you please elaborate a bit how I can useIcarusto do the
translation from Verilog to LIF (the format's details don't matter,
actually its not a standard format and stands for List Intermediate
Format)? I mean how do I get the output after the elaboration stage so
that I can process it?

There is some documentation for this feature here:

http://iverilog.wikia.com/wiki/Using_Loadable_Target_API

The idea is that the core compiler does the parse and elaboration,
including resolving libraries and doing all the yucky error handling,
then invokes a code generator to write out the checked result in
the desired form. There is a "vvp" code generator that generates
the run-time simulation, there is a "null" code generator that
does nothing and there is a "stub" code generator that I use for
debugging.

The web page above (part of the largerIcarusVerilog documentation)
should be enough to get you started with a code generator, including
installing an example. The ivl_target.h header file that comes withIcarusVerilog defines the complete API for accessing the elaborated
design, so you can read that to get an idea how complete it is.

The purpose of this API is exactly to allow people to write
translators that take advantage of all the parsing/error checking
that the compiler already does. All you have to do is write a
function that scans the design at your leisure and does whatever
you want with it.
- --
Steve Williams "The woods are lovely, dark and deep.
steve aticarus.com But I have promises to keep,http://www.icarus.com and lines to code before I sleep,http://www.picturel.com And lines to code before I sleep."
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Click to expand...
Hi Steve,

I am trying to use the loadable API feature of Icarus and so I am
trying to read the ivl_target.h file as instructed in the wikia entry.
I want to understand which functions to call in my personal target
module to generate the code. Can you please tell me if I want to
access the elaborated design of something simple as a 1 bit half
adder, what functions should I use. I don't come from a computer
science background and so am finding it very confusing to understand
the comments in the ivl_target.h file of v0.8.

module dff_ck_en (data, clk, reset, en, q);
input data, clk, reset, en;
output q;
reg q;
always @ (posedge clk or negedge reset)
if (~reset)
q = 1'b0;
else if (en)
q = data;
endmodule


What I want basically is to use this feature of Icarus to construct a
translator from Verilog to a personal format of mine. The conversion
if done by hand would look like

(module
(input (data, clk, reset, en))
(output (q))
(reg (q))
( always (@ (or (posedge clk) (negedge reset)))
(if (not reset)
(equal q 1'b0)
(else if (en)
(equal q data)
)
)
)

I have the rules of conversion from verilog to my format with me. If I
have access to the elaborated design I can generate the output in my
desired format. Ofcourse if you have any other suggestion for doing it
except starting from scratch and using lex and yakk, I will be glad to
hear it too.

So if you can just give me a small example of a loadable target module
(if you can use this example of a flip flop it would be great because
it has if-else statements etc too) I will have a better idea of how to
go about it.
I have read the manual and know how to compile and insert the loadable
module, I just am having problems writing the module.

Respectfully,
Shamik
 
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Shamik wrote:
I am trying to use the loadable API feature of Icarus and so I am
trying to read the ivl_target.h file as instructed in the wikia entry.
I want to understand which functions to call in my personal target
module to generate the code. Can you please tell me if I want to
access the elaborated design of something simple as a 1 bit half
adder, what functions should I use. I don't come from a computer
science background and so am finding it very confusing to understand
the comments in the ivl_target.h file of v0.8.
Click to expand...

You start by implementing a "target_design" function. See as an
example the tgt-null target in the Icarus Verilog sources. This
function will be called by the compiler, and you treat it as your
"main" for your code generator. The ivl_design_t object is your
handle to the whole design.

Then you have a bunch of functions that you can apply to ivl_design_t
objects to get information about your design. A good start is the
function "ivl_design_root" that gets you a root scope for your
design, which is an ivl_scope_t object.

And so on and so forth. Each type defined in ivl_target.h has
functions that you can use to access bits from instances of that
type.

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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