Verilog Intger data type

[trescot@gmail.com]

I have a question regarding verilog integer data types. The default
integer size is 32 bit in Verilog. Can we extend it? In VHDL we can
have something like,

Max_Time : in integer range 0 to 255;

How do we express this in Verilog?


Thanks
Trescot

 

[Jonathan Bromley]

On Mon, 23 Jul 2007 21:20:06 -0000,
"trescot@gmail.com" <trescot@gmail.com> wrote:

I have a question regarding verilog integer data types. The default
integer size is 32 bit in Verilog. Can we extend it? In VHDL we can
have something like,

Max_Time : in integer range 0 to 255;

How do we express this in Verilog?

You can't. Instead, define your own signed or unsigned vectors
of appropriate width. "integer" is really only a special name
for "reg signed [31:0]".

(Yes, I know there are some issues that make this not
exactly true, especially in Verilog pre-2005; but it's close.)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.