Verilog input ports

[kbhar]

Hi,

Is it legal to define input ports as wires ? For instance,

module (input clock,
input a,
input b,
output c
);

wire clock, a, b;

The compiler doesn't complain, so how does one justify not defining
them as wires? And if the definition is redundant, then is there a
different scenario for behavioral or structural models (one needs
inputs to be defined as wires and the other not)?

Thanks
kbhar

 

[Jonathan Bromley]

On Mon, 9 Mar 2009 07:14:52 -0700 (PDT), kbhar wrote:

Is it legal to define input ports as wires ?

Yes.

For instance,

module (input clock,
input a,
input b,
output c
);

wire clock, a, b;

The compiler doesn't complain, so how does one justify not defining
them as wires?

"wire" is, in the ordinary way of things, the default.
You can change that default using the `default_nettype
directive:

`default_nettype wand;

module (input a, /// a is now a 'wand'
input b, /// but b is a 'wire' - see below
...
);
wire b;

You can also say
`default_nettype none
in which case the "wire" declaration becomes necessary.

And if the definition is redundant, then is there a
different scenario for behavioral or structural models (one needs
inputs to be defined as wires and the other not)?

No. Verilog can't tell the difference between "behavioural"
and "structural"; it's all Verilog. The difference is only
one of definition or convention.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[unfrostedpoptart]

On Mar 9, 7:14 am, kbhar <kanchan.devarako...@gmail.com> wrote:

Hi,

Is it legal to define input ports as wires ? For instance,

module (input clock,
             input a,
             input b,
             output c
             );

wire      clock, a, b;

The compiler doesn't complain, so how does one justify not defining
them as wires? And if the definition is redundant, then is there a
different scenario for behavioral or structural models (one needs
inputs to be defined as wires and the other not)?

Single-bit wires don't need to be declared in Verilog. In Verilog
2001, they added default_net_type, which you can set to none to
require declaring them all. This can be helpful to avoid miss-typing
names of signals throughout a file. Many people (most) don't do this
because they want to save typing. I think they'll end up spending as
much, or more, time fixing bugs causes by this

Also, it's good you're using the ANSI-style module header, but you
should't mix this with declaring the signal types separately. Try
this:

module (input wire clock, // please add comments to say what the
signal does!
input wire a,
input wire b,
output wire c // or reg, or, even better if you've got
SystemVerilog support, logic
);